A method for implementing an array signal processor for phased array radars. The array signal
processor can receive planar array antenna inputs and can process it. It is based on the application of Adaptive
Digital beam formers using FPGAs. Adaptive filter algorithm used here is Inverse Q-R Decomposition based
Recursive Least Squares (IQRD-RLS) [1] algorithm. Array signal processor based on FPGAs is suitable in the
areas of Phased Array Radar receiver, where speed, accuracy and numerical stability are of utmost
important. Using IQRD-RLS algorithm, optimal weights are calculated in much less time compared to
conventional QRD-RLS algorithm. A customized multiple FPGA board comprising three Kintex-7 FPGAs is
employed to implement array signal processor. The proposed architecture can form multiple beams from planar
array antenna element