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Application Notes If you want to do a bit more reading about how our FPGAs lend themselves to a broad number of applications, we recommend these application notes. XAPP1206: BOOST SOFTWARE PERFORMANCE ON ZYNQ-7000 AP SOC WITH NEON http://www.xilinx.com/support/documentation/application_notes/xapp1206-boost-sw-performance-zynq7soc-wneon.pdf Generally speaking, a CPU executes instructions and processes data one-by-one. Typically, designers achieve high performance by using high clock frequencies, but semiconductor technology imposes limits on this technique. Parallel computation is the next strategy typically employed to improve CPU data-processing capability. The single-instruction, multiple-data (SIMD) technique makes it possible to process multiple data in one or just a few CPU cycles. NEON is the advanced SIMD engine found in the dual-core ARM® Cortex™-A9 processor that’s part of the Xilinx® Zynq®-7000 All Programmable SoC. Effective use of NEON—which is specialized for parallel data computation on large data sets—can boost software performance in your design. In this application note, author Haoliang Qin introduces four methods for improving software performance and cache efficiency using NEON on a Cortex-A9 processor core. They include optimizing assembler code and using NEON intrinsics, NEON-optimized libraries and compiler-optimized automatic vectorization. He also details ways to improve data exchanges among the CPU, cache and main memory. Software optimization is a complex topic. To realize optimal performance from hardware, you must apply all of these techniques together and properly balance them, Qin says.
XAPP1208: BITSLIP IN LOGIC http://www.xilinx.com/support/documentation/application_notes/xapp1208-bitslip-logic.pdf I/O logic in Xilinx UltraScale™ devices refers to the dedicated I/O-handling components located between the I/O buffers and the general interconnect. The I/O logic setup in UltraScale devices provides faster I/O handling, better jitter specifica66
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tions and more functionality than in previous device families. However, it omits some functionality available in the I/O logic of the 7 series and Virtex®-6 FPGAs, such as Bitslip. This application note by Marc Defossez describes a Bitslip solution implemented in general interconnect that you can use in UltraScale devices as well as in previous device architectures. The reference design implements the Bitslip function and extends the basic functionality with several extra options. This Bitslip reference design performs the same functionality as the native Bitslip functionality embedded in the ISERDES of 7 series and Virtex-6 FPGAs, but goes beyond those implementations by offering extra options not available in solutions based on those two device families. The general interconnect must be used when the functionality available in this design is needed in a 7 series or Virtex-6 FPGA design. Therefore, this Bitslip reference design meets the requirements and goals of Bitslip offered in previous device families.
XAPP1203: IMPLEMENTATION OF SIGNAL PROCESSING IP ON ZYNQ-7000 AP SOC TO POST-PROCESS XADC SAMPLES http://www.xilinx.com/support/documentation/application_notes/xapp1203-post-proc-ip-zynq-xadc.pdf This application note is a follow-up and companion to the white paper “Efficient Implementation of Analog Signal Processing Functions in Xilinx All Programmable Devices” (WP442), which proposes a simple and easy design flow for implementing analog signal-processing functions in Xilinx FPGAs and All Programmable SoCs, leveraging Xilinx All Programmable Abstractions. Here, authors Mrinal J. Sarmah and Cathal Murphy describe in detail how to leverage the concepts outlined in the white paper to build signal-processing IP cores and a complete mixed-signal system easily on the Zynq-7000 All Programmable SoC. Third Quarter 2014