XPERTS CORNER
You will want to check that you have adequately and completely constrained your design without having overconstrained it. will automatically be forward-annotated to the Vivado® Design Suite placeand-route (P&R) tools to further ensure that timing will be met. The synthesis tool can assist you with the challenging task of setting up presynthesis constraints. On your to-do list will be to: 1. Identify clocks 2. Identify and create clock groupings and clock relationships 3. Constrain clocks 4. Constrain design inputs and outputs 5. Define multicycle paths and false paths You will want to check that you have adequately and completely constrained your design without having overconstrained it. Overconstraining will result in longer run-times and potentially, the reporting of false critical paths. Be sure to specify multicycle and false paths, and to set constraints on derived clocks (define_path_delay, define_false_path).
Setting up an initial constraints file for Vivado flows Since constraints setup can be daunting, the synthesis software can help by providing an initial constraints template with basic constraints and syntax that can act as a starting point. For example, in the Synplify synthesis software, run the TCL utility to create an initial FDC file for a specific design: TCL: create_fdc_template Figure 1 shows an example of the constraints (.fdc) file that this process will generate. In this example, you can see that key items, such as declaring clocks, clock group (relationship between clocks) and input/output delays, have been taken care of. Best practices for constraints setup in Vivado Design Suite flows When setting up constraints in Vivado Design Suite flows, be sure to do the following: • Define all primary clocks on input ports or nets connected to input ports.
• Define clocks on the black-box output pins. • Define generated clocks on nets. • Don’t define gated clocks. • Provide correct clock constraints: Don’t overconstrain, and be sure to place unrelated (aka asynchronous) clocks in separate clock groups. • Define timing exceptions such as false paths and multicycle paths. Hint: In Vivado Design Suite, clock constraints should be applied as close to the source clock as possible, not on the BUFG, as was the case in Xilinx ISE® Design Suite flows. Ensuring that your constraints are correct We recommend four constraints verification techniques during the design setup phase. To give you an idea of the types of constraints checks that are worthwhile, let’s look at the checks that Synplify software performs.
###==== BEGIN Clocks – {Populated from tab in SCOPE, do not edit) create_clock –name {clock} [get_ports {p:clock}] –period 10 –waveform {0 5.0} ###==== END Clocks - {Populated from tab in SCOPE, do not edit) ###==== BEGIN Inputs/Outputs - {Populated from tab in SCOPE, do not edit) set_input_delay {p:porta[7:0]} 1 –clock {c:clock} –add_delay set_input_delay {p:portb[7:0]} 1 –clock {c:clock} –add_delay … set_output_delay {p:porto[7:0]} .5 –clock {c:clock} –add_delay … ###==== END Inputs/Outputs - {Populated from tab in SCOPE, do not edit) ###==== BEGIN Registers - {Populated from tab in SCOPE, do not edit) … set_clock_groups –disable –asynchronous –name {clock_group} –group {clock} –comment {Source clock clock group} Figure 1 – An initial Synplify synthesis input constraints file takes care of basic clock setup and I/O constraints requirements. The constraints will be forward-annotated to the Vivado place-and-route tool. 54
Xcell Journal
Third Quarter 2014