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Application Notes If you want to do a bit more reading about how our FPGAs lend themselves to a broad number of applications, we recommend these application notes. XAPP1179: USING TANDEM CONFIGURATION FOR PCIE IN THE KINTEX-7 CONNECTIVITY TRD http://www.xilinx.com/support/documentation/application_ notes/xapp1179-tandem-config-pcie.pdf The PCI Express® specification requires the PCIe® link to be ready to connect with a peer within 120 milliseconds after power is stable. Meeting this requirement is a challenge for large FPGAs using flash memory for configuration due to the size of the programming bitstream and the configuration rates available. The Tandem Configuration approach from Xilinx® is a practical way to reduce FPGA configuration time to meet the 120-ms PCIe link-training requirement. This application note by Sunita Jain, Mrinal Sarmah and David Dye shows how to use the Tandem PROM and the Tandem PCIe configuration methods with the Kintex®-7 Connectivity Targeted Reference Design (TRD) running on the KC705 evaluation board with a Kintex-7 XC7K325T FPGA. The design describes the adjustments made to the TRD to accommodate Tandem Configuration. Using this approach, the base bitstream size, and therefore the initial configuration time, is reduced by more than 85 percent when using Tandem PROM and more than 80 percent when using Tandem PCIe.
XAPP1184: PIPE MODE SIMULATION USING INTEGRATED ENDPOINT PCI EXPRESS BLOCK IN GEN2 X8 CONFIGURATION http://www.xilinx.com/support/documentation/application_ notes/xapp1184-PIPE-mode-PCIe.pdf Verifying designs involving high-speed serial protocols such as PCI Express can be complex and time-consuming. Many verification projects utilize third-party bus functional models (BFMs) to reduce the complexity of the verification process and to speed up the time spent running the actual simula64
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tion. Gigabit transceivers are a particular problem for verification, since the GTs often consume a significant number of processor cycles to simulate. For this reason, and because GTs typically have little impact on the behavior of the upper PCI Express layer functionality, many verification projects bypass them for much of their verification and only simulate with GTs to validate the design at the end of a project The PHY Interface for the PCI Express Architecture (PIPE) is a specification for linking the PCI Express block and the GTs. This application note by K. Murali Govinda Rao and A. V. Anil Kumar provides a way to connect the PIPE interface of the PCI X-actor BFM (in root complex mode) from Avery Design Systems to the PIPE interface of a Xilinx 7 series FPGA Integrated PCI Express Endpoint Block. When configured with the proper options, the Xilinx PCIe Endpoint will have PIPE ports at the core’s top level. You can connect these ports to the X-actor RC BFM to bypass simulating with the GTs. While this application note demonstrates specific connections to the Avery BFM, it can also serve as a model for how to connect other third-party BFMs to the Integrated PCIe Endpoint Block through the PIPE interface. PIPE-mode simulation is very useful for reducing the simulation time during verification of complex PCI Express applications.
XAPP1097: IMPLEMENTING SMPTE SDI INTERFACES WITH ARTIX-7 FPGA GTP TRANSCEIVERS http://www.xilinx.com/support/documentation/application_ notes/xapp1097-smpte-sdi-a7-gtp.pdf The serial digital interface (SDI) family of standards from the Society of Motion Picture and Television Engineers (SMPTE) is widely used in professional broadcast studios and video production centers to carry uncompressed digital video, along with embedded ancillary data such as multiple audio channels. The Xilinx SMPTE SD/HD/3G-SDI LogiCORE™ First Quarter 2014