XAMPLES...
Application Notes If you want to do a bit more reading about how our FPGAs lend themselves to a broad number of applications, we recommend these application notes. XAPP1086: DEVELOPING SECURE AND RELIABLE SINGLE-FPGA DESIGNS WITH XILINX 7 SERIES FPGAS USING THE ISOLATION DESIGN FLOW http://www.xilinx.com/support/documentation/application_notes/xapp1086-secure-single-fpga-using-7s-idf.pdf This application note targets FPGA designers working on security or safety-critical designs—specifically, singlechip cryptography, avionics, automotive and industrial applications—using the Xilinx® Isolation Design Flow (IDF). Author Ed Hallett explains how to use IDF to implement isolated functions in a single Xilinx 7 series or 7 series Q (defense-grade) FPGA or in a Zynq®-7000 All Programmable SoC. Functions might include red/black logic, redundant Type-I encryption modules or logic that processes multiple levels of security. Designers will also learn how to verify the isolation using the Xilinx Isolation Verification Tool (IVT). Xilinx developed the Isolation Design Flow to allow independent functions to operate on a single chip. The ability to develop a safe and secure single-chip solution containing multiple isolated functions is made possible through Xilinx partition technology. Special attributes such as SCC_ISOLATED provide controls to achieve the isolation needed for meeting certifying-agency requirements. With this application note, designers can develop a fail-safe single-chip solution that meets all security requirements for high-grade, highassurance applications. The Kintex®-7 FPGA family is currently supported for the IDF. For an in-depth look at the Isolation Design Flow, see also XAPP1085 (http://www.xilinx.com/support/documentation/application_notes/xapp1085-7s-isolation-designflow-ise-14-4.pdf). XAPP1170: ZYNQ-7000 ALL PROGRAMMABLE SOC ACCELERATOR FOR FLOATING-POINT MATRIX MULTIPLICATION USING VIVADO HLS http://www.xilinx.com/support/documentation/application_notes/xapp1170-zynq-hls.pdf Matrix multiplication is used in nearly every branch of applied mathematics. For example, it is essential in beamforming, which is the process of phasing a receiving antenna 66
Xcell Journal
digitally by computer calculation in modern radar systems. This application note describes how to use Vivado® highlevel synthesis (HLS) to develop a floating-point matrixmultiplication accelerator with an AXI4-Stream interface and connect it to the Accelerator Coherency Port (ACP) of the ARM® CPU in the Zynq-7000 All Programmable SoC. Vivado HLS can quickly implement the accelerator, which is modeled in the C/C++ code, and optimize it into an RTL design. The solution is then exported as a pcore connected with an automatically created AXI4-Stream interface to the ACP. Authors Daniele Bagni, Juanjo Noguera and Fernando Martinez Vallina used Xilinx Platform Studio (XPS) to design the programmable logic hardware, including the matrix-multiplier peripheral, the DMA engine and an AXI timer. They used the Software Development Kit (SDK) to design the processing system software to manage the peripherals. The driver application is a 32x32 matrix-multiplication core optimized for 32-bit floating-point accuracy using Vivado HLS.
XAPP1160: AXI CHIP2CHIP REFERENCE DESIGN FOR REAL-TIME VIDEO APPLICATION http://www.xilinx.com/support/documentation/application_notes/xapp1160-c2c-real-time-video.pdf The LogiCORE™ IP AXI Chip2Chip is a soft Xilinx core that bridges between AXI systems for multidevice system-onchip solutions. This application note by Saambhavi Vajjiravelu Baskaran and Vamsi Krishna provides a setup demonstrating real-time video traffic across Kintex-7 FPGA and Zynq-7000 All Programmable SoC boards. The AXI Chip2Chip core provides connectivity across two Xilinx boards using FMC connector cables. The reference design includes two embedded systems created with the Xilinx Platform Studio (XPS) v14.5 tool, which is part of the ISE® Design Suite: System Edition. The axi_chip2chip_v3_00_a core implements a video system in which the Test Pattern Generator (TPG) creates test patterns. Two instances of the core are instantiated, one as a master and one as a slave. Complete XPS and SDK project files are provided. Fourth Quarter 2013