X P L A N AT I O N : F P G A 1 0 1
Data converters that interface with Xilinx FPGAs are fast embracing the new JESD204B high-speed serial link. To use this interface format and protocol, your design needs to take some basic hardware and timing issues into account. n most designs today, parallel low-voltage differential signaling (LVDS) is the interface of choice between data converters and FPGAs. Some FPGA designers still use CMOS as the interface in designs with slower converters. However, the latest highspeed data converters and FPGAs are migrating from parallel LVDS and CMOS digital interfaces to a serialized interface called JESD204B, a new standard developed by the JEDEC Solid State Technology Association, an independent semiconductor engineering trade organization and standardization body. As converter resolution and speed have increased, the demand for a more efficient interface has grown. This interface is the critical link between FPGAs and the analog-to-digital or digital-to-analog converters that reside beside them in most system designs. The JESD204B interface brings this efficiency to designers, and offers several advantages over preceding interface technologies. New FPGA designs employing JESD204B enjoy the benefits of a faster interface to keep pace with the faster sampling rates of converters. Also, a dramatic reduction in pin count leads to smaller package sizes and fewer trace routes, making board designs a little less complex.
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Third Quarter 2013
All this does not come for free. Each type of interface—including JESD204B—comes with design issues such as timing concerns. The specifics differ somewhat, but each interface brings its own set of parameters that designers must analyze properly to achieve acceptable system performance. There are also hardware choices to be made. For example, not all FPGAs and converters support the JESD204B interface. In addition, you must be up to date on parameters such as the lane data rate in order to select the appropriate FPGA. Before exploring the details of the new JESD2904B interface, let’s take a look at the other two options that designers have long used for FPGAto-converter links: CMOS and LVDS. CMOS INTERFACE In converters with sample rates of less than 200 megasamples per second (MSPS), it is common to find that the interface to the FPGA is CMOS. A high-level look at a typical CMOS driver shows two transistors, one NMOS and one PMOS, connected between the power supply (VDD) and ground, as shown in Figure 1a. This structure results in an inversion in the output, and to avoid it, Xcell Journal
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