COVER STORY
logic system. The key features the processing system supports are: • Dynamic RAM interface—doubledata-rate SDRAM, supporting both DDR2 and DDR 3 standards, including LPDDR2. • Static RAM interfaces—support for SRAM devices along with NAND, NOR and QSPI flash memories. • Communications interfaces—UART, CAN, I2C, SPI, USB, Gigabit Ethernet and SD/SDIO. • General-purpose I/O—support for up to four 32-bit general-purpose I/Os. With the exception of the DRAM link, the remaining interfaces utilize the Multiuse I/O, a bank of 54 I/O pins that you can assign to different functions as required. This does, of course, mean you cannot implement all peripherals at once. However, you can extend this interface into the programmable logic if you wish. Communication between the processing system and programmable logic sides is comprehensive, and includes: • Advanced Microcontroller Bus Architecture (AMBA®) and Advanced eXtensible Interface (AXI), with both master and slave interfaces, including direct links to external DDR and on-chip memory. In addition, the Accelerator Coherency Port (ACP) provides coherent access to the CPU memory space from the programmable logic side. • Extended Multiuse I/O, which allows you to increase the number of processing system peripherals by using programmable logic I/O. • Direct memory access and interrupts, including 16 interrupts from the PL to the PS, along with four DMA channels. • Four clocks and resets from the processing system to the programmable logic. 10
Xcell Journal
Figure 1 – The Base System Builder for the AXI bus
Zynq configuration differs from the process of configuring many of the previous families of Xilinx FPGAs, even those that contained hard macro processors like the Virtex®-2 Pro, Virtex-4 and Virtex-5 families. Within the Zynq system, the processing side is the master and therefore boots following a normal software boot process, loading in the application from nonvolatile memory and then either executing in place or crossloading the application into faster DDR memory using a more complex boot loader. The programmable logic side of the Zynq loads via the Processor Configuration Access Port (PCAP), which allows both partial and full configuration. As always, you can also configure the device through the JTAG interface. Because of this added complexity, the Zynq device has more mode pins than you normally find on an FPGA to support all of these various configuration methods.
WHAT TOOLS DO WE NEED? Creating a system-on-chip (SoC) requires a little more effort than developing a logic-based FPGA design. However, it is still pretty straightforward and the tool chain provides good guidance. To create a Zynq SoC design you will need four tools at a minimum: Xilinx Platform Studio, the ISE® Design Suite, Xilinx’s Software Development Kit (SDK) and iMPACT. Xilinx Platform Studio is the place where you create your processing system, be it PowerPC®, MicroBlaze™ or, in this case, the Zynq PS. Here, in XPS, you define the configuration, interfaces, timing and address ranges—everything needed to generate a processor system. The output from this process is an HDL netlist defining your system. Most FPGA engineers are familiar with ISE. This Xilinx tool chain takes your HDL design, including the XPS netlist, and generates the required bit file. The Software Development Kit, First Quarter 2013