Xcell Journal issue 81
The autumn 2012 edition of Xcell Journal magazine details Xilinx’s monumental accomplishments at 28nm that have allowed it to jump a Generation Ahead of the competition by fielding All Programmable SoCs, 3D ICs and FPGAs as well as a new tool suite to program the devices. The issue also includes several informative how-to and design methodology articles from the Xilinx’s technical staff and the user community.
XTRA, XTRA What’s New in the Vivado 2012.3 Release? The Vivado™ Design Suite 2012.3 is now available, at no additional cost, to all Xilinx® ISE® Design Suite customers that are currently in warranty. The Vivado Design Suite provides a highly integrated design environment with a completely new generation of system-to-IC-level features, including high-level synthesis, analytical place-and-route and an advanced timing engine. These tools enable developers to increase design integration and implementation productivity. THE VIVADO DESIGN SUITE 2012.3 ■ New multithreaded place-and-route technology accelerates design productivity even further on multicore workstations, with 1.3x faster runtimes on a dual-core processor and 1.6x faster runtimes on a quad-core. ■ Vivado extends the portfolio of very popular Targeted Reference Designs (TRD) for the Kintex™-7 and Virtex®-7 families to further accelerate designer productivity. • The Kintex-7 FPGA Base TRD showcases the capabilities of Kintex-7 FPGAs through a fully integrated PCIe® design that delivers 10-Gbit/second (Gbps) performance end-to-end using a performance-optimized DMA engine and DDR3 memory controller. • The Kintex-7 FPGA Connectivity TRD delivers up to 20 Gbps of 68 Xcell Journal performance per direction featuring a dual network interface card (NIC) with a Gen2 x8 PCIe endpoint, a multichannel packet DMA, a DDR3 memory for buffering, a 10G Ethernet MAC and a 10GBASE-R standard compatible physical-layer interface. • The Kintex-7 FPGA Embedded TRD offers a comprehensive processor subsystem complete with Gigabit Ethernet, DDR3 memory controller, display controller and other standard processor peripherals. • The Kintex-7 FPGA DSP TRD includes a high-speed analog interface with digital up- and downconversion overclocked to run at 491.52 MHz. • You can find a complete list of Vivado Design Suite-supported TRDs at http://www.xilinx.com/ ise/design_tools/support.htm. NEW DEVICE SUPPORT The following devices will be in production fully supporting design with both the Vivado Design Suite 2012.3 and ISE Design Suite 14.3: • Kintex-7 70T, 410T, 480T, 420T, 355T, 325T (Low Voltage), 160T (Low Voltage) • Virtex-7 X485T (Low Voltage) The following devices will be in general engineering sampling (ES) supporting both Vivado Design Suite 2012.3 and ISE Design Suite 14.3: • Virtex-7 X690T The following devices will be in general ES in Vivado Design Suite 2012.3: • Virtex-7 X1140T, 2000T • Artix™-7 100T, 200T The following devices will be in initial ES in Vivado Design Suite 2012.3: • Virtex-7 H580T For further information regarding the release, please visit http://www.xilinx.com/support/documentation/sw_ manuals/xilinx2012_2/ug910-vivado-getting-started.pdf. WHAT IS THE VIVADO DESIGN SUITE? It’s all about improving designer productivity. This entirely new tool suite was architected to increase your overall productivity in designing, integrating and implementing with the 28-nanometer family of Xilinx All Fourth Quarter 2012