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experiments at GateRocket, we performed all simulation runs presented on the same machine. [3] OPTION 1: REMOVING THE SERDES MODELS One common approach to simulating designs with FPGA serdes models is to eliminate the models altogether and replace them with shells that connect the parallel core-side data directly from source to destination. This is typically done by “scoping in” to the simulation model to drive the serdes model’s parallel outputs directly and monitor its parallel core-side inputs directly from transactors in the testbench. This approach is diagrammed in Figure 4. This approach has the advantage of eliminating the need to develop complex serial transactors, at the expense of accuracy of dynamics and function of the serial link. For example, any impact on the core-side logic of serialization or deserialization time will not be properly modeled; nor will errors occurring during deserialization. For the simple 8b10b example in Figure 1, this is a straightforward solution, because the serdes elements are used solely to transport parallel data from end to end. No control information passes through the serial link. By contrast, using this approach with the Xaui design in Figure 2 requires substantial knowledge of the configuration and I/O of the core side of the serdes. Simply looping transmit data and the “comma character” control signals to the receiver is not sufficient, as the Xaui core logic expects transitions through synchronization states on the control outputs of the GTP_DUAL serdes elements. This highlights the need for accurate serdes models. It’s easy to build core-side circuitry that will succeed with simplified models but fail when connected to the accurate behavior of real physical devices. Creating a model that passes logic simulations while scoping around the minimum required set of core-side signals will not guaranThird Quarter 2011
tee a functional device once the FPGA is built and operating in the lab. Verifying the interface operation has two sides: verifying the core-side logic and interface, and verifying the serdes operation itself. The scoping method does nothing to verify the configuration or implementation of the serdes itself. Using this approach with the design in Figure 1 results in very fast simulations; testing completes in less than 1 second. The same approach applied to the Xaui design in Figure 2 delivers 18second simulations. The modeling effort is trivial (minutes to hours) for
the 8b10b design and more substantial (days to weeks) for the Xaui design. OPTION 2: USING A SECOND SERDES Another approach to functionally verifying FPGA serdes designs is to use an FPGA serdes simulation model in the testbench as a transactor. This has the benefit of rapid development time, at the expense of the time it takes to run each simulation, since the load on the simulator from the serdes models doubles. The basic approach (diagrammed in Figure 5) is to instantiate the serdes
Entity
Percent of CPU Load
Simulation Time in Seconds
GTP_DUALs
71%
41.8
Xaui core
11%
6.5
Transactors
10.6%
6.3
Testbench
7.4%
4.4
Table 1 – Simulation profile of a Xaui core
TESTBENCH TRANSACTOR
DATA GENERATE AND CAPTURE FUNCTION
FPGA
SERIAL TRANSMIT
SERIAL RECEIVE
SERDES SIMULATION MODEL
SERDES SIMULATION MODEL
SERIAL RECEIVE
SERIAL TRANSMIT
FPGA RECEIVE LOGIC
FPGA TRANSMIT LOGIC
TESTS
Figure 5 – Connection of testbench serdes
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