COVER STORY
Xilinx’s Zynq-7000 Extensible Processing Platform family mates a dual ARM Cortex-A9 MPCore processor-based system on the same device with programmable logic and hardened IP peripherals, offering the ultimate mix of flexibility, configurability and performance. ilinx has just unveiled the first devices in a new family built around its Extensible Processing Platform (EPP), a revolutionary architecture that mates a dual ARM Cortex™-A9 MPCore processor with lowpower programmable logic and hardened peripheral IP all on the same device (see cover story, spring 2010 issue of Xcell Journal, http://www.xilinx.com/publications/ archives/xcell/Xcell71.pdf). In March of this year, Xilinx officially announced the first four devices of what it has now dubbed the Zynq™7000 EPP family. Implemented in 28-nanometer process technology, each Zynq-7000 device is built with an ARM dual-core Cortex-A9 MPCore processing system equipped with a NEON media engine and a double-precision floating-point unit, as well as Level 1 and Level 2 caches, a multimemory controller and a slew of commonly used peripherals (Figure 1). While FPGA vendors have previously fielded devices with both hardwired and soft onboard processors, the Zynq7000 EPP is unique in that the ARM processor system, rather than the programmable logic, runs the show. That is, Xilinx designed the processing system to boot at power-up (before the FPGA logic) and to run a variety of operating systems independent of the programmable logic fabric. Designers then program the processing system to configure the programmable logic on an as-needed basis. With this approach, the software programming model is exactly the same as in standard, fully featured ARM processor-based systems-onchip (SoCs). Previous implementations required designers to program the FPGA logic to get the onboard processor to work. That meant you had to be an FPGA designer to use the devices. This is not the case with the Zynq-7000 EPP.
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Second Quarter 2011
Xcell Journal
9