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Interfacing the signal-processing FPGA with the real world requires the use of an analog-to-digital or digital-to-analog converter. nce it’s performed the task it was designed to do, an FPGAbased system next has to interface with the real world, and as every engineer knows, the real world tends to function around analog as opposed to digital signals. That means conversion is going to be required to and from the digital domain from the analog realm. Just as you face a plethora of choices in selecting the correct FPGA for the job at hand, so too will you find an abundance of riches when choosing the correct ADC or DAC for a system. The first thing to establish is the sampling rate you will need to convert the signal. This parameter will drive not only the converter selection but will also impact your FPGA choice as well, to ensure the device can address the processing speed and logic footprint required. The sampling rate of the converter needs to be at least twice that of the signal being sampled. Therefore, if you need to sample a signal at 50 MHz, your sampling rate must be at least 100 MHz. Otherwise the converted signal will be aliased back upon itself and will not be correctly represented. This aliasing is not always a bad thing; in fact, if the converter bandwidth is wide enough, you can employ the aliasing to fold signals back into the usable bandwidth.
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ADC AND DAC KEY PARAMETERS Analog-to-digital converters are constructed by many different techniques. Some of the most common are flash, ramp and successive approximation. • Known for their speed, flash converters use a series of scaled analog comparators to compare the Third Quarter 2012
input voltage against a reference voltage; ADCs use the outputs of these comparators to determine digital code. • Ramp converters utilize a freerunning counter connected to a digital-to-analog converter, comparing the output of the DAC against the input voltage. When the two are equal, the count is held. • Successive-approximation converters are an adaptation of ramp converters and also utilize a DAC and a comparator against the analog input. However instead of counting up, the SAR converter determines whether the analog representation of the count is above or below the input signal, allowing a trial-anderror-based approach to determining the digital code. Digital-to-analog converters also come in several implementations, some of the most common being binary-weighted, R-2R ladder and pulsewidth modulation. • Binary-weighted is one of the fastest DAC architectures. These devices sum the result of individual conversions for each logic bit. For example, a resistor-based DAC will switch resistors on or out depending upon the current code. • R-2R ladder converters use a structure of cascaded resistors of value R-2R. Due to the ease with which precision resistors can be produced and matched, these DACs are more accurate than the binary-weighted types.
• Pulse-width modulation, the simplest type of DAC architecture, passes the PWM waveform through a simple low-pass analog filter. These devices are commonly used in motor control but also form the basis for delta-sigma converters. Many manufacturers of specialist devices have developed their own internal conversion architectures to provide the best possible performance in specific areas depending upon the intended use. Each of these varieties has pros and cons relating to the speed of conversion, accuracy and resolution. As when selecting an FPGA, you will look at the number of I/Os, I/O standards supported, clock management, logic resources and memory, along with parameters specific to the device type: the maximum sampling rate, signal-to-noise ratio (SNR), spurious-free dynamic range (SFDR) and effective number of bits (ENOB). The sampling frequency is pretty simple; it’s the maximum rate at which an ADC can digitize its input. SNR represents the ratio of the signal to the noise level, which is assumed to be uncorrelated with the input signal. You can determine the SNR theoretically using the equation SNR = 6.02N + 1.76 dB where N is the resolution. This equation is valid for a full-scale sine wave. You can determine the actual SNR during system test by taking a fast Fourier transform (FFT) of the output and measuring between the value of the input signal and the noise floor. The SFDR, meanwhile, is the ratio between the input signal and the next Xcell Journal
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