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XTRA, XTRA Xilinx Tool & IP Updates Xilinx is continually improving its products, IP and design tools as we strive to help designers work more effectively. Here, we report on the most current updates to the ISE® Design Suite development environment, as well as on updates to Xilinx’s IP. Product updates offer significant enhancements and new features to four versions of the ISE Design Suite: the Logic, Embedded, DSP and System Editions. Keeping your installation of ISE up-to-date is an easy way to ensure the best results for your design. On May 8, 2012, Xilinx released ISE Design Suite 14.1. It will be available from the Xilinx Download Center at In all the editions of ISE Design Suite 14.1, the Zynq™-7000 EPP family, including XA Zynq7000, are now public access. ISE supports their programming by means of bitstream generation. Likewise, defense-grade 7 series FPGA families are now public access. In addition, the Virtex®-7 XT FPGA family now supports bitstream generation. Finally, Artix™-7 FPGA GTPE2 support is now available in this latest version of ISE. For more information or to download a free 30-day evaluation of ISE Design Suite, visit ISE DESIGN SUITE: LOGIC EDITION Front-to-Back FPGA Logic Design Latest version number: 14.1 Date of latest release: May 2012 Previous release: 13.4 Revision highlights: Mentor Graphics’ ModelSim & Questa advanced simulator integration: The PlanAhead™ design tool now allows you to choose these Mentor Graphics products as the target simulator in the project settings. Simulation requires library compila68 Xcell Journal tion, which you can accomplish through the Tcl command “compxlib,” enabling you to have multiple simulation file sets with their own sets of properties. Embedded Development Kit integration: The PlanAhead design tool can now create and add Xilinx Platform Studio subsystems to a project through the .xmp source type. Double-clicking on the .xmp source type launches Platform Studio to generate and customize the embedded subsystem. ISE DESIGN SUITE: EMBEDDED EDITION Integrated Embedded Design Solution Latest version number: 14.1 Date of latest release: May 2012 Previous release: 13.4 Revision highlights: All ISE Design Suite editions include the enhancements listed above for the Logic Edition. The Embedded Edition now also offers Zynq-7000 EPP support for bare-metal and Linux-based product development, as well as MicroBlaze™ processor updates. Other enhancements include the following. New low-latency interrupt mode: The controller directly supplies the interrupt vector, reducing the latency response by as much as 10x depending on the system design. New swap instructions: Instructions for byte and halfword swapping help support endianness conversions between AXI big-endian and AXI little-endian. Additional device support: Xilinx has now validated the MicroBlaze processor across the 7 series of products. System cache: The Embedded Edition adds a new embedded system cache IP peripheral between the MicroBlaze processor and external memory controller for AXI-based systems. The MicroBlaze processor uses this system cache IP core as Level 2 cache, resulting in lower latency and faster performance depending on multiple system factors, design type or connection points. Second Quarter 2012

Xcell Journal issue 79

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