XAMPLES...
Application Notes If you want to do a bit more reading about how our FPGAs lend themselves to a broad number of applications, we recommend these application notes.
XAPP588: VIRTEX-5QV FPGA EXTERNAL CONFIGURATION MANAGEMENT http://www.xilinx.com/support/documentation/ application_notes/xapp588_v5qv_ex_config_mgmt.pdf The Xilinx® Virtex®-5QV device is high in logic density and radiation-hardened by design, and contains 12-transistor (12T) configuration memory cells. The result is the fastest and largest FPGA available for high-reliability space applications. This makes the Virtex-5QV FPGA the programmable logic device of choice for orbital applications. This FPGA has an extremely low upset rate of five events per year. However, if needed, designers can implement configuration management to ensure reliable functionality over long operational periods by periodically performing a soft reboot, as Y.C. Yang explains in this application note. Orbital applications carry the risk that high-energy charged particles will cause a single-event upset (SEU) in a programmable logic device’s configuration memory. When an SEU affects memory cells essential to the design, the result can impact the application functionality. Additionally, an SEU in the FPGA control circuitry can cause a single-event functional interrupt (SEFI). Since both of these scenarios are undesirable, designers need a way to resume normal and expected functionality in the form of configuration management. The configuration management scheme outlined in this application note involves using an external device to monitor and scrub the Virtex-5QV FPGA to mitigate SEU and SEFI effects. This external device—which is assumed to be a space-qualified FPGA or ASIC, although it could also be a microprocessor—performs SEU detection and cor66
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rection, partial reconfiguration, blind scrubbing, and SEFI detection and mitigation. The reference design is based on the configuration monitor IP used during radiation testing of the Virtex-5QV device. Because a Virtex-II Pro FPGA is the external configuration manager in the Xilinx test apparatus, Yang implemented the reference design using ISE® 10.1.03 software. Nonetheless, the reference code should be 100 percent portable to later versions of ISE, since it infers design primitives and is synthesizable in XST.
XAPP553: SCALABLE SERDES FRAMER INTERFACE (SFI-S) FOR 7 SERIES FPGAS http://www.xilinx.com/support/documentation/application_ notes/xapp553-scalable-serdes-framer-interface.pdf The Scalable Serdes Framer Interface (SFI-S) is an Optical Internetworking Forum (OIF) standard that defines the electrical connections between devices on a typical optical-communications line card. An n-bit-wide SFI-S configuration contains n data channels and one control channel for interface skew compensation. This application note by Julian Kain describes a 10-data-channel SFI-S design targeting Xilinx 7 series FPGAs using GTX or GTH serial transceivers to implement an aggregate 111.8-Gbit/second bidirectional interface. The hardware-verified Verilog HDL reference design provides significant skew compensation and fine-grained control of skew tracking, and the Verilog HDL source can be readily modified if necessary. A synthesizable example design with PRBS31 generator and checker logic enables simple simulation and a hardware demonstration of the reference design. Second Quarter 2012