X C E L L E N C E I N C O M M U N I C AT I O N S
High-Level Synthesis Tool Delivers Optimized Packet Engine Design AutoESL enabled the creation of an in-fabric, processor-free UDP network packet engine. by Nathan Jachimiec, PhD R&D Engineer Agilent Technologies Technology Leadership Organization nathan_jachimiec@agilent.com Fernando Martinez Vallina, PhD Software Applications Engineer Xilinx, Inc. vallina@xilinx.com
14
Xcell Journal
igabit Ethernet is one of the most ubiquitous interconnect options available to link a workstation or laptop to an FPGA-based embedded platform due to the availability of the hardened triEthernet MAC (TEMAC) primitive. The primary impediment in developing Ethernetbased FPGA designs is the perceived processor requirement necessary to handle the Internet Protocol (IP) stack. We approached the problem using the AutoESL high-level synthesis tool to develop a high-performance IPv4 User-Datagram Protocol (UDP) packet transfer engine. Our team at Agilent's Measurement Research Lab wrote original C source code based on Internet Engineering Task Force requests for comments (RFCs) detailing packet exchanges among several protocols, namely UDP, the Address Resolution Protocol (ARP) and the Dynamic Host Configuration Protocol (DHCP). This design implements a hardware packet-processing engine without any need for a CPU. The architecture is capable of handling traffic at line rate with minimum latency and is compact in logic-resource area. The usage of AutoESL makes it easy to modify the user interface with minimum effort to adapt to one or more FIFO streams or to multiple RAM interface ports. AutoESL is a new addition to the Xilinx® ISE® Design Suite and is called Vivado™ HLS in the new Vivado Design Suite (see cover story).
G
Second Quarter 2012