The magazine of record for the embedded computing

The magazine of record for the embedded computing industry

January 2008

www.rtcmagazine.com

COM Express: SMALL MODULES TAKE ON

BIG JOBS Ethernet Switching Brings Speed and Density Home Small Modules Move DAQ Closer to the Signals IP–The Soul of Programmable Logic

An RTC Group Publication

Kontron and the Kontron logo are registered trademarks of Kontron AG. All other trademarks are the property of their respective owners. Š2008 Kontron America, Inc.

ETXexpress-MC ETXexpress-WPM

1-888-294-4558 - info@us.kontron.com — EMEA: +49 0 800 7253756 - Asia: +886 2 2910 3532

microETXexpress-PM

COM Express: SMALL MODULES TAKE ON BIG JOBS

21 Desktop Chassis, Industrial Computer (CompactRIO) and USB Single-Module Carrier

26 Some of the form-factors specified in the JTRS HMS inventory

TABLEOF CONTENTS

38 GHz Digital Receiver PMC/XMC Module and Dual Multiband Tranceiver with FPGA

January 2008

Departments

Technology in Context

COM Express Solutions 6 COM Express− A Living Standard for Modular Solutions 12 Industry Insider 9Latest Developments in the Embedded Marketplace Editorial The Illusion of Security

Christine Van De Graaf, Kontron

Solutions Engineering

44

Products & Technology Newest Embedded Technology Used by Industry Leaders

56

News, Views and Comment Embedded Computer Business on Fast Track Despite Economic Forecasts

Ethernet Switching

16

The Best Network Seems Like No Network Iain Kenney, SMC Networks

Industry Insight Data Acquisition

More with Less 20 Doing (Hardware, That Is)

Brett Burger, National Instruments

24

Data Acquisition: Harnessing Small Modules with Flexible I/O Scott Hames, GE Fanuc

SYSTEM INTEGRATION IP for Programmable Logic

the Use of FPGAs with Optimized IP 28 Enabling Tom Hill, Xilinx

Developers Empowered by the FPGA Revolution 34 Software Eric Schneider, Eridon

Featured Products

Digital Receiver PMC/XMC Module offers 2- or 4- Channel 38GHz Oppreation GE Fanuc Intelligent Platforms

Multiband Transceiver with 38Dual FPGA Delivers Improved A/D Performance Pentek

Industry Watch Data-Oriented Architecture

Oriented Architecture: 40Data Loosely Coupling Systems into “Systems of Systems”

Rajive Joshi, Ph.D, Real-Time Innovations Inc.

Digital Subscriptions Avaliable at www.rtcmagazine.com/digital

January 2008

2

C OTS Your product

cPCI PMC VME PCI ATX choice of OS

January 2008 Publisher PRESIDENT John Reardon, johnr@r tcgroup.com EDITORIAL DIRECTOR/ASSOCIATE PUBLISHER Warren Andrews, warrena@r tcgroup.com

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Standard & custom designs

COPY EDITOR Rochelle Cohn

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To Contact RTC magazine: HOME OFFICE The RTC Group, 905 Calle Amanecer, Suite 250, San Clemente, CA 92673 Phone: (949) 226-2000 Fax: (949) 226-2050, www.rtcgroup.com EASTERN SALES OFFICE The RTC Group, 96 Dudley Road, Sudbury, MA 01776 Phone: (978) 443-2402 Fax: (978) 443-4844 Editorial Office Warren Andrews, Editorial Director/Associate Publisher 39 Southport Cove, Bonita, FL 34134 Phone: (239) 992-4537 Fax: (239) 992-2396 Tom Williams, Editor-in-Chief 245-M Mt. Hermon Rd., PMB#F, Scotts Valley, CA 95066 Phone: (831) 335-1509 Fax: (408) 904-7214

Published by The RTC Group Copyright 2007, The RTC Group. Printed in the United States. All rights reserved.

All related graphics are trademarks of The RTC Group. All other brand and product names are the property of their holders.

January 2008

EDITORIAL

January 2008

The Illusion of Security

by Tom Williams, Editor-in-Chief

A

t a recent conference, I was treated to an in-depth examination of computer security issues, accompanied by excerpts from the recent Bruce Willis film, “Live Free or Die Hard,” which depicts how the U.S., along with its economic and physical infrastructure, can be brought to a complete halt by a concerted attack on our computer networks. The upshot of the conference was the realization that our computer networks are presently woefully insecure and it is possible to make them much more secure than they currently are. But—at least in my own interpretation—the idea of total security is an illusion.

I am reminded of what is possibly the last short story written by the early 20th-century author, Franz Kafka called “The Burrow.” The story is about a non-specific animal that has built itself a huge, labyrinthine burrow in which to safely store its food and to keep itself safe from enemies and intruders. At first, all seems well, but the animal frets constantly about the entrance, which, though camouflaged with moss, cannot be completely concealed, especially when the animal enters or leaves the burrow. Then one day the animal awakens inside its burrow and becomes aware of a barely audible hissing sound coming from no specific location.

After that, all the animal’s efforts are directed at abating that sound, but to no avail. The last sentence of the (interestingly) unfinished story is, “but everything remained unchanged.” Note that the animal is never actually attacked by an enemy; it is a story about self absorption and insecurity.

In contrast, there have been real attacks on our computer networks, some of which appear to have been probing exercises that originated in China. The threat of identity theft is also very real. I will not go into a litany of threats, which can be found elsewhere, but it is now clear that there are enormous efforts underway by both government and private entities to produce more secure networked systems. These include advanced encryption, secure operating systems and hardware-based security technology. Currently, however, most networked systems, which are commonly based on Windows or Linux operating systems, are typically rated by what are known as the “common criteria” evaluation assurance levels (EAL) at EAL4 on a scale from 1 to 7. Level 4 is designated for users who “require a moderate to high level of independently assured security in a conventional commodity.”

They are NOT secure against a determined or sophisticated attack, nor can they economically be made so. Period.

This does not mean that there are not critical points, such as power plants and military installations that are not being made very much more secure than your PC. But given the enormous deployed base of moderately secured systems, the uncertainty about how they are all actually connected and how the various networks are managed, how will we ever know how secure ev-

January 2008

erything is? The answer, of course, is that we cannot. However, over time, it is quite possible that the situation will improve with much more secure “separation kernel” style operating systems being made commercially available as OEM products that can be integrated with commercial operating systems to provide much higher levels of security—perhaps as high as EAL6+.

Still, the only realistic view of security is how much effort a determined enemy is willing to devote to hacking into a given site. You want to keep your data secure? Great. Lock your system in a vault, don’t connect it to a network and don’t turn it on. Beyond that, it’s a relative game. In addition, entities like the NSA don’t really want your or my system to be absolutely secure because they still want to have some option for access. Whatever the merits of that, if there is some kind of back door, it can also be discovered by others. According to security lore, there are PhDlevel experts in certain countries constantly studying our systems and looking for vulnerabilities, which they catalog against the day they may want to attack. Whenever one is discovered and fixed, it gets crossed off the list. But it’s a long list.

As our lives become ever more intertwined with networked systems ranging from telecom systems to small devices deployed in industry, businesses and homes, we make a compromise with security. There is much that can, should and is being done to improve this situation and bring not only better operational security but more peace of mind. But it requires constant effort, analysis and innovation and no one will ever be able to certify with absolute assurance that it is completely secure. There is still that annoying hissing sound. . .

g Embedded World in Nurember ld show

Wor I will be attending the Embedded ruar y.

Feb of k wee last the rg in Nurembe press to allow Unfortunately, the show does not t means Tha ite. on-s only pre- register online, but ple peo s pres h whic w kno exhibitors do not ointments are attending and can’t make app g at or bitin in advance. Any companies exhi ld like to set wou who ld attending Embedded Wor at: me tact con se up meetings, plea (831) 335 -1509 or at: tomw@r tcgroup.com.

GE Fanuc Intelligent Platforms

There’s life in the old dog yet.

You can even get him to do things he didn’t used to be able to do.

VMEbus technology may be 25 years old - which, by industry standards, makes it a pretty old dog - but at GE Fanuc Intelligent Platforms, you’d never know. That’s because our commitment to VME has seen us continually push the boundaries of what it can do, to the point where it is still capable of fulfilling the requirements of today’s most demanding applications.

Take, for example, what we’re doing with VXS – the way forward for VME users who want to leverage their investment in legacy systems to the maximum and take advantage of what serial switched fabrics bring to the table. The DSP220 VXS multiprocessor and CRX800 VXS Serial RapidIO managed switch bring industry-leading performance: the DSP220 features four single- or dual

core Freescale™ PowerPC® 8641 system-on-chip nodes and an XMC slot, while the CRX800 provides 22 ports of x4 Serial RapidIO at speeds up to 3.125Gbits/second per lane. Both are available in six ruggedization levels.

And whether you’re planning to deploy on VME, on VXS or on VPX, GE Fanuc Intelligent Platforms’ AXIS Advanced Multiprocessor Integrated Software development environment means you develop just once – not three times.

AT GE Fanuc Intelligent Platforms, our state of the art VPX, VXS and VME solutions mean that you can indeed teach an old dog new tricks.

DSP220

CRX800

www.gefanucembedded.com

© 2008 GE Fanuc Intelligent Platforms, Inc. All rights reserved.

G e t o n t h e F a s t Tr a c k Don’t let custom requirements slow you down.

Our existing products and custom design expertise help our clients to quickly meet complex design requirements.

VadaTech is a leader in AdvancedTCA, AMC, cPCIe, VXS, XMC and custom board-level technology.

Dedicated to leading-edge technology for the most demanding applications; we pride ourselves on our extraordinary capability to quickly create designs in response to our customer requirements.

Our service to the aerospace and telecommunications markets has resulted in a quickly growing line of AdvancedTCA, AMC, cPCIe, VXS, XMC and custom boards for processing, communication, storage, and platform interoperability.

ATC800

Sprint past the competition with VadaTech as your teammate!

W W W . V A D A T E C H . C O M T E L 1 . 7 0 2 . 8 9 6 . 3 3 3 7

IndustryInsider january 2008

Nanowire Battery Holds Ten Times the Charge of Existing Ones Researchers at Stanford University have found a way to use silicon nanowires to reinvent the rechargeable lithium-ion batteries that power laptops, iPods, video cameras, cell phones and countless other devices including, soon, hybrid and electric vehicles.

The new version, developed through research led by Yi Cui, assistant professor of materials science and engineering, produces 10 times the amount of electricity of existing lithium-ion, known as Li-ion, batteries. A laptop that now runs on battery for two hours could operate for 20 hours, a boon to ocean-hopping travelers.

“It’s not a small improvement,” Cui said. “It’s a revolutionary development.”

The breakthrough is described in a paper, “High-Performance Lithium Battery Anodes Using Silicon Nanowires,” published online Dec. 16 in Nature Nanotechnology, written by Cui, his graduate chemistry student Candace Chan, and five others.

The greatly expanded storage capacity could make Li-ion batteries attractive to electric car manufacturers. Cui suggested that they could also be used in homes or offices to store electricity generated by rooftop solar panels.

“Given the mature infrastructure behind silicon, this new technology can be pushed to real life quickly,” Cui said.

The electrical storage capacity of a Li-ion battery is limited by how much lithium can be held in the battery’s anode, which is typically made of carbon. Silicon has a much higher capacity than carbon, but also has a drawback.

Silicon placed in a battery swells as it absorbs positively charged lithium atoms during charging and then shrinks during use as the lithium is drawn out of the silicon. This expand/shrink cycle typically causes the silicon (often in the form of particles or a thin film) to pulverize, degrading the performance of the battery.

Cui’s battery gets around this problem with nanotechnology. The lithium is stored in a forest of tiny silicon nanowires, each with a diameter one-thousandth the thickness of a sheet of paper.

The nanowires inflate four times their normal size as they soak up lithium. But, unlike other silicon shapes, they do not fracture.

Research on silicon in batteries began three decades ago. Chan explained: “The people kind of gave up on it because the capacity wasn’t high enough and the cycle life wasn’t good enough.

And it was just because of the shape they were using. It was just too big, and they couldn’t undergo the volume changes.”

Then, along came silicon nanowires. “We just kind of put them together,” Chan said.

For their experiments, Chan grew the nanowires on a stainless steel substrate, providing an excellent electrical connection. “It was a fantastic moment when Candace told me it was working,” Cui said.

Cui said that a patent application has been filed. He is considering formation of a company or an agreement with a battery manufacturer. Manufacturing the nanowire batteries would require “one or two different steps, but the process can certainly be scaled up,” he added. “It’s a well understood process.”

Report Shows Developers Consider Embedded Linux as Dependable as RTOSs

Embedded Market Forecasters has released a new research report entitled, “Embedded Linux Total Cost of Development Analyzed.” Based on interviews with more than 1,300 embedded developers, the new study compares the outcomes of hundreds of design projects that used embedded Linux to those that used commercial RTOSs, and further compares project outcomes using commercial embedded Linux with non-commercial “roll your own” embedded Linux. The findings are intended to provide device manufacturers with empirical information to support decision making on embedded OS selection.

According to the new EMF report: • Embedded Linux has achieved design parity with commercial RTOSs for most projects.

Embedded Linux design outcomes are consistent with the outcomes of projects using operating systems from commercial RTOS vendors.

• Use of a commercial embedded Linux OS is more effective than a non-commercial “in-house” Linux development undertaking. In spite of the fact that in-house Linux development projects typically involve much less complexity than projects that use commercial embedded Linux and RTOSs, 15.9% fewer inhouse embedded Linux projects meet the pre-design expectation levels achieved by developers using commercial Linux and RTOSs. • Embedded Linux can be used in a mission-critical environment that requires MILS (Multiple Independent Levels of Security) or EAL (Evaluation Assurance Level) certification January 2008

Industry Insider

EventCalendar 02/05-07/08

03/17-20/08

AFCEA West 2008 San Diego, CA www.afcea.org

VON.x San Jose, CA www.von.com

02/08-10/08

03/25/08

So. California Linux Expo Los Angeles, CA www.socallinuxexpo.org

Real-Time & Embedded Computing Conference Dallas, TX www.rtecc.com

02/12/08 Real-Time & Embedded Computing Conference Atlanta, GA www.rtecc.com/atlanta2008

02/19/08 Real-Time & Embedded Computing Conference Huntsville, AL www.rtecc.com/huntsville2008

02/21/08 Real-Time & Embedded Computing Conference Melbourne, FL www.rtecc.com/melbourne2008

03/03-07/08 SD West 2008-01-14 Santa Clara, CA www.sdexpo.com

03/11-12/08 Mountain View Alliance Communications Ecosystem Conference San Francisco, CA www.mvacec.com

03/17-18/08

03/27/08 Real-Time & Embedded Computing Conference Houston, TX www.rtecc.com

04/08-10/08 ROBOBusiness Conference & Expo Pittsburgh, PA www.robobusiness.com

04/14-18/08 Embedded Systems Conference San Jose, CA www.com-egevents.com

04/29/08 Real-Time & Embedded Computing Conference Chicago, IL www.rtecc.com

04/30 – 05/02/08 Small Fuel Cells for Commercial & Military Applications Atlanta, GA www.knowledgefoundation.com

VoiceCon Orlando 2008 Orlando, FL www.voicecon.com

If your company produces any type of industry event, you can get your event listed by contacting sallyb@rtcgroup.com.

This is a FREE industry-wide listing.

10

January 2008

or POSIX conformance, when used in protected memory under a certified RTOS. A stable and application-proven embedded Linux design could be directly incorporated within a mission-critical application that requires MILS or EAL certification.

Embedded Market Forecasters’ “Embedded Linux Total Cost of Development Analyzed” report can be downloaded at www.embeddedforecast.com.

PICMG and CP-TA Complete Second Interoperability Workshop

The Communications Platforms Trade Association (CPTA) and PICMG have teamed up again in Chicago to host a joint Interoperability Workshop, demonstrating structured testing to industry profiles. PICMG has hosted several Interoperability Workshops in the past, and this is the second time they’ve partnered with CP-TA. Open to members of PICMG and CP-TA, a total of 19 different companies participated in the workshop to test products, designed to PICMG specifications, for interoperability issues. While some AdvancedTCA testing was done, the workshop focused mainly on MicroTCA and AMC. The results of the workshops are confidential to the companies participating so that the testing can take place in an environment focused on learning and resolving issues.

“We are encouraged to see the continued maturation of AMC and MicroTCA products at these workshops and see how the interop testing helps companies address interoperability issues early in the design process,” said Joe Pavlat, PICMG President.

“With the anticipated release of the PICMG Release 3.0 AdvancedTCA specification, we will offer testing for AdvancedTCA, AMC and MicroTCA at our next event.”

“At this event, CP-TA demonstrated for the first time new

thermal and manageability test tools for AMC and MicroTCA,” said Nirlay Kundu, CP-TA Compliance Work Group Chair. “We definitely saw the most interest for MicroTCA testing. Many vendors in the early stage of the development process were able to take advantage of the structured testing. It was exciting to use the tools to find bugs early in the design process and enable companies to address interoperability issues right away.”

“CP-TA demonstrated that it is on track on its current roadmap of delivering a MicroTCA interoperability specification in Q1 of 2008,” said Todd Keaffaber, CP-TA Technical Work Group Chair.

During the event CP-TA and Polaris Networks demonstrated the new MicroTCA Tester. This test tool, to be released in the near future, incorporates the IPMB analyzer. DegreeC also demonstrated prototype thermal test tools for AMC and MicroTCA. PICMG and CP-TA will hold future events together and provide testing for products based on the PICMG 3.0 Release 3.0.

Cavium Networks Teams with Broadcom to Offer Set of Switching Reference Designs

Cavium Networks has announced a set of reference designs targeted at intelligent switching and broadband applications.

These reference designs will utilize Cavium’s market-leading Octeon Multi-core MIPS64 processor family along with Broadcom’s widely adopted enterprise class StrataXGS and home/SMB RoboSwitch Gigabit Ethernet switches, and Fastpath networking software. The reference designs aim to reduce engineering development cost and time-tomarket for intelligent enterprise switches, Layer 4+ switches and SOHO/SMB routers.

The scalable set of reference designs using Cavium and Broadcom silicon addresses

Industry Insider

the need for pre-integrated, optimized and validated reference designs addressing enterprise and SMB/home markets.

Enterprise Class Reference Designs To enable tightly integrated design with seamless interoperability, Broadcom has licensed its HiGig protocol to Cavium Networks. The HiGig protocol enhances Ethernet switching beyond industry standards with features such as stacking and QoS. Cavium Networks recently introduced Octeon processors and follow-on processors with 10 Gigabit interfaces integrate hardware acceleration that supports HiGig protocol and enable intelligent switching applications.

Additionally, Broadcom will utilize Cavium Octeon processors in its enterprise reference designs as a control plane and services processor, supporting the complete portfolio of StrataXGS Ethernet switches, which are industry-leading, widely deployed merchant silicon switching solutions.

SMB/Home Reference Designs Broadcom is also utilizing Cavium Octeon processors in its SMB switching reference designs as a gateway host processor combined with Broadcom’s RoboSwitch Gigabit Ethernet Switches and Fastpath networking software.

Curtiss-Wright and Sigma Partner to Integrate Physical Layer Switches and Test Automation

Curtiss-Wright Controls Embedded Computing and Sigma Technologies & Resources have announced that they have partnered to offer integrated physical layer switch and test automation software solutions for enterprise network lab automation applications. Sigma announced that it has developed software libraries to integrate its SigmationTF test automation software with Curtiss-Wright’s GLX family of switches, includ-

ing the GLX4000 series of nonblocking, multi-protocol physical layer switches.

Sigma’s SigmationTF software is a comprehensive test automation framework designed for testing TCP/IP-based network products. It provides automated regression test methodologies to free test engineers from doing costly, time-consuming and error-prone manual testing. SigmationTF automates the large number of repetitive tests typically required during the test phase of the product life cycle, and later, the regression tests needed as software versions evolve.

The GLX4000 can support up to 288 ports and up to 2.5 Tb/s in switching capacity. The company offers SFP- and XFP-based interface cards for flexibility and support of a wide range of serial digital protocols including 1/2/4 Fibre Channel, 10G Ethernet, 10/100/1000 Ethernet, SONET and Firewire.

New SCOPE Profiles Cover AdvancedMC and MicroTCA

The SCOPE Alliance recently announced the availability of the following two new documents: • AdvancedMC Profile, version 1.0 • MicroTCA Profile, version 1.0.

These profiles describe the preferred implementation options for their respective technologies.

They represent the consensus view of the SCOPE Alliance, (which consists of seven major network equipment providers and many suppliers of standard platform elements). SCOPE hopes that by providing implementation guidance in the form of these profiles, it can reduce the variability that currently exists in AdvancedMC and MicroTCA elements, improve interoperability and facilitate high-volume ecosystems.

Each profile has an overview, a set of definitions and a profile table describing SCOPE’s preferred implementation requirements. There are also some gaps identified. A gap is a technical issue that in SCOPE’s view could benefit from some additional refinement in the AdvancedMC or MicroTCA specifications.

SCOPE believes that these profiles could serve as guidelines for many different users of the PICMG specifications. Suppliers of elements (like a chassis, modules, or software) may find the profiles to be a good source of consensus marketing requirements. Network equipment providers may use these profiles as guidelines as they refine their platform architectures and prepare RFXs for suppliers. Network operators may find the profiles valuable as they plan the capabilities of their network elements. The documents can be found at: www.picmgeu.org/pages/t_interesting_articles.htm.

SDR Forum Launches Task Group on Transceiver Subsystem Interfaces

The Software Defined Radio Forum has announced the launch of a worldwide task group on transceiver subsystem interfaces (TSI). Created under the umbrella of the SDR Forum Technical Committee, the new task group will be dedicated to facilitating industry convergence on open specifications supporting the interface between the radio frequency (RF) front end and baseband processing/modem subsystems in reconfigurable radio products.

The TSI task group’s initial objective will be to expand upon the work done by the European End-to-End Reconfigurability program and other related efforts to define standard transceiver application programming interfaces (API) for use by radio equipment manufacturers in the commercial, public safety and

defense domains. These APIs will act as an abstraction layer for the transceiver hardware, facilitating the insertion of new or updated physical-layer waveform applications and air interface standards while the radio is in operation and, at the same time, improving the portability of these applications and standards from radio to radio.

As a part of this effort, the TSI task group will—to ensure support—evaluate the proposed transceiver API against the various lower-level transceiver interface specifications and standards that have been developed for the commercial and defense wireless markets over the past several years. This evaluation will include the Reference Point 3 specification developed under the OBSAI (Open Base Station Architecture Initiative), the DigRF Interface specification under development by the MIPI (Mobile Industry Processor Interface) Alliance, the VITA Radio Transport draft standard developed by the VITA Standards Organization as VITA 49, and the CPRI (Common Public Radio Interface). One important outcome of this activity will be the revised submission of the transceiver API in response to the OMG’s (Object Management Group) Digital IF request-forproposal for additional follow-on standardization.

January 2008

11

Technology InContext

COM Express Solutions

COM Express – A Living Standard for Modular Solutions Finally, an industrial standard that doesn’t obsolete itself when silicon changes and is still solid enough to meet longevity requirements of critical embedded applications.

by C hristine Van De Graaf Kontron

T

here are few embedded computing technology people these days who have not heard the words COM Express mentioned at least once when discussing what platform to develop around for the next-generation solution. In the unlikely event that this is the first time you are hearing about COM Express, here is the concept in a nutshell: The COM Express (COM.0) specification is controlled by the PCI Industrial Computer Manufacturers’ Group (PICMG). The standard defines a computer-on-module based on serial differential signaling technology that incorporates interfaces including PCI Express, Serial ATA, USB 2.0, LVDS and Serial DVO. Paired with advanced processors and chipsets, COM Express modules provide the highest performance and I/O bandwidth available in computer-on-modules (COMs). Some key features of COM Express to keep in mind as we discuss it are as follows: • PCI Express – the elemental data path • Gigabit Ethernet – for high connectivity • USB 2.0 – for fast peripherals • Serial ATA – for fast drives • ACPI – for optimized power management

12

January 2008

CPU NorthBridge SouthBridge

Video Audio LAN USB

Analog Power Full Custom Headers Board

Figure 1

CPU

Video Audio LAN USB

NorthBridge South- Embedded Bridge Module Analog Power

Carrier Board

Headers

Custom Motherboard vs.

Computer-on-Module.

Building on the successes of ETX (Embedded Technology eXtended) computer-on-modules that hit the embedded scene over five years ago, the intention of the COM Express standard is to give embedded designers a highly integrated standard computing core to insert at the heart of their systems, paired with a customized baseboard where expansion and application-specific features are designed in. This is the optimal choice, where as before computer-on-modules, embedded system designers more often than not found themselves engaged in the development of full custom solutions in order to meet their unique requirements. This allows designers to focus more on their core competencies and the custom solution design rather than on the features in the pro-

cessing engine. The small, rugged designs of computer-on-modules allow them to fit where other solutions don’t, mechanically, economically and functionally. Additionally, COM-based solutions allow designers to respond more quickly to demand fluctuations, competitive forces and new technologies (Figure 1).

But, why is COM Express needed when other computer-on-modules such as ETX, XTX, SOM, etc. already are available? The initiators of the COM Express standard (Kontron, Intel and others) recognized that the market wanted to take advantage of newer technologies such as PCI Express and Serial ATA that were coming onto the scene. COM Express modules allow for a smooth transition from PCI, ISA and IDE (legacy technology) to PCI Express, SATA and more.

Support for Gigabit Ethernet and USB 2.0 (advanced communications technologies) allows the use of data more immediately.

An example of this would be where medical personnel at a hospital can prepare to care for a patient while that patient is being transported to the hospital, because the emergency medical team is able to quickly transmit 3-D scans and vital stats. Additionally, the support of PCI Express graphics rather than older

Technology InContext

AGP graphics greatly improves the images that doctors have to review when evaluating a patient’s condition. More advanced treatment while en route also may become possible. There is no bottleneck in the transmission of data to the user nor in the development of the product in the first place, as much of the hard work of the hardware development, design and testing is done by the module manufacturer leaving the medical application developer to focus his or her attention on the software and special features of the tool.

Today the offering of COM Expresscompatible modules encompasses various sizes and pin-outs. There are five defined

by PICMG (Table 1) as well as processor and chipset variations. The most recent addition, a nano-sized (55 mm x 84 mm) COM Express module as proposed by Kontron, is intended to bring the benefits of the COM Express standard to advanced and highly mobile applications whose lowpower and size requirements are not met by the other small COMs such as X-board, XTX, etc. Although these open standards offer a good range of features and some with low-power variations, they have been limited with respect to interoperability with existing systems and scalability.

Type 1 Gigabit Ethernet Serial ATA AC97 USB 2.0 PCI Express LVDS 5v Standby VGA Power LPC PCI IDE Note:

Table 1

Micro

Nano

Basic

Extended

Dimensions PCI Express Lanes Serial ATA Memory

95mm x 95mm

55mm x 84mm

95mm x 125mm

155mm x 110mm

0 to 2 lanes

2 or more lanes

2 or more lanes

2 or more lanes

Yes

Yes

Yes

Yes

1x Socket DDR2 SO-DIMM

On-board

Up to 2x Socket Up to 2x Socket DDR2 SO-DIMM or Desktop DIMM Mini-DIMM

USB 2.0 Ethernet PICMG COM Express Standard

Yes

Yes

Yes

Yes

10/100

10/100/1000

10/100/1000

10/100/1000

Pending

Pending

Yes

Yes

Figure 2

COM Express comparison chart.

The proposed nanoETXexpress specification is targeted to deliver extremely power-saving computer-on-modules with mid- to high-performance x86 technology on a footprint that is a mere 55 mm x 84 mm. This is 39 percent of the original COM Express module Basic form-factor 125 x 95 mm footprint and 51 percent of microETXexpress (95 mm x 95 mm). This new COM form-factor follows the PICMG COM Express standard and will be 100 percent compliant with the COM.0 Type 1 connector. The locations of the identically mapped pin-outs will also be 100 percent COM.0 compliant. As such, apType 2

Type 3

plications such as stationary point-of-sale (POS) systems built around one of the first COM Express modules could be updated to use a new nanoETXexpress module to achieve greater power efficiency. With a few tweaks, the unit possibly could become mobile, opening up a greater customer base for the POS application.

Key features planned for inclusion in the nanoETXexpress specification include multiple PCI Express lanes and USB 2.0 ports, Serial ATA support, advanced graphics capabilities such as dual 24-bit LVDS channels and Gigabit Ethernet. It will represent a good option for mobile, Type 4

Type 5

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes • Single connector • Lowest cost pin-out • First nanoETXexpress modules will follow this pin-out

• Includes IDE, PCI and up to 22 PCI Express • The “Base-Line” pin-out • Most of today’s COM Express solutions follow this pin-out

Yes • I ncludes PCI support and up to 3 Gigabit Ethernet ports • No IDE supported • Example of solution following this pin-out is the Kontron ETXexpressWPM module

• Includes IDE support and up to 32 PCI Express lanes • No PCI support

• Support for up to 32 PCI Express lanes and 3 Gigabit Ethernet ports • No IDE support and no PCI support • The “Legacy Free” pinout

COM Express Five Defined Pin-out Types.

January 2008

13

Technology InContext

rugged applications because the specification includes onboard DRAM and flash instead of SO-DIMM sockets for ruggedness, an extreme low-power Ethernet controller for overall lowest power consumption and a wide range power supply input of 4.75 to 14 VDC. The goal of the nanoETXexpress specification is to build PCI Expressbased computer-on-modules on the smallest possible form-factor. Many new ap-

plications that will benefit from the nano size include handheld units for medical, mobile data solutions and other emerging applications that have not been possible as of yet due to size restrictions. New silicon that will be coming from the industry leaders in 2008 and 2009 is already set to support this trend (Figure 2).

Additionally, work has begun at PICMG to update the COM Express standard. A subcommittee has been organized

to review the standard as a whole and jointly develop a design guide for COM Express baseboards that will ensure the continued interchangeability of modules independent of which vendor has supplied the COM Express module. The subcommittee will address issues outlined in both the PnP Design Guide from Congatec and the COM Express Extension Design Guide from the COM Industrial Group.

Other key items that will be discussed by the subcommittee include: • Multiplexed graphics pin-out to support PEG, SDVO, TMDS and Display Port in order to fit the needs of all the chipsets that will appear in the next few years • Extended power supply range from 8.5V DC to 18V DC instead of 12V DC only • Onboard thermal control and BIOS implementations with smart battery support • Two dedicated GPIO pins for energy management functions • New obligatory support of legacy interfaces via super I/O chips By bringing out new interface technology, COM Express modules have met the design challenges of application segments that previously required full-custom single board computer solutions for a diverse array of embedded applications.

The addition of nanoETXexpress as a compatible embedded computing technology solution following the elements of the COM Express standard will make it possible for designers to take many formerly stationary applications and make them not only more power efficient, but make them much more mobile as well.

Existing COM solutions and those that will become available as the COM Express specification continues to adapt to new technologies and market demands, will fulfill the needs of existing advanced embedded applications and those that are yet to be imagined.

Kontron Poway, CA. (858) 667-0877. [www.kontron.com].

14

January 2008

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solutions engineering

ethernet switching

The Best Network Seems Like No Network Strategic network optimization with 10 Gigabit Ethernet technology makes connections invisible. Network-wide or strategically placed, 10GbE is an important component of the overall Ethernet performance networking strategy, and there are multiple ways to deploy 10GbE to get the best “bang for the buck” in any network.

by I ain Kenney SMC Networks

W

ith so many bandwidth-intensive applications in use that reach across networks—both local and wide-area—the only downside to upgrades has been cost. Speed and bandwidth availability vary in most networks from 3 Mbits/s or less across standard Wi-Fi (802.11b) connections, to 10 Gigabits in high-performance corporate LANs. With bandwidth, though, it doesn’t need to be all-or-nothing.

While some networks warrant 10 Gigabit Ethernet (10GbE) all the way, for many others a close analysis of network usage can uncover high-return locales for high-speed technology—places where pockets of 10GbE technology can affect overall network performance so that all users get the most from their connections, and the network budget doesn’t get depleted. The broad range of high-speed, high-bandwidth solutions available today make it possible for more companies to leverage standardscompliant 10GbE in their networks. It doesn’t have to be cost-prohibitive. As the 10GbE networking market continues to evolve and redistribute, a breadth of products to address today’s demands ensures that deployment of 10GbE is a practical solution, when and where it makes a difference—whether for the

16

January 2008

Legend

Building B

PoE 1G Fiber 10G Fiber 1G Copper Wireless SMC6152L2

SMC2555-AG Building C

10G Core

SMC6152L2

Firewall Servers

Figure 1

Internet

The most common application for expensive—to purchase and to deploy—10GbE connectivity has been building-to-building connection.

New 10GBase-T technology makes it reasonable to put more 10GbE into more places for even freer bandwidth.

whole network, or in high-demand portions of it (Figure 1).

Relieving Bottlenecks at the Server

In the server room or data center, the benefits of 10 Gigabit connections are clear: interconnecting busy processing,

application and storage servers with as high a bandwidth connection as is available has a huge impact on efficiency.

Relieving bottlenecks that occur at 10 or 100 Mbit/s server connections by replacing the overloaded segments with 10GbE uplinks can make the network as a whole move data faster. 10/100/1000

Which Way do You Want Your 10Gb Ethernet?

2500MB/sec 10G b 250MB/se

c 1Gb

Software Stack Conventional NIC Technology

Silicon Stack Critical I/O XGE

Silicon Stack Technology from Critical I/O. 10Gb Ethernet at Wire Speed.

[Problem] You’re expecting 10Gb Ethernet to deliver a whole lot more performance to your embedded system. But what if you invest in it and get no gain at all? The performance of nearly all existing 1Gb applications are limited by the software overhead associated with the TCP/IP protocol stack. This bottleneck is in the software stack, not the network hardware.

So, simply upgrading to 10Gb pipes will not improve your system’s performance.

[Solution] Unlike conventional Ethernet interfaces or processor-based “offload” products, Critical I/O’s Silicon Stack technology eliminates this inherent bottleneck by offloading protocol processing to silicon; thereby achieving sustained line-rate performance, microsecond latency, and rock-solid deterministic behavior. And, Silicon Stack is 100% compliant with Ethernet standards, allowing you to leverage existing applications and hardware.

XGE Silicon Stack Ethernet vs. Software-based Stack

Software Stack 10Gb

1Gb

10Gb

40 varies with protocol

250

2500

1Gb Throughput max sustained rate in MBytes/sec Host Overhead

Very High

Latency

125 μsec

Determinism max sustained rate Reliability

Silicon Stack

Horrible ± 200 μsec Poor when under heavy load

Very Low 12 μsec

5 μsec

Rock Solid ± 1 μsec Excellent under all load conditions, no dropped data

SOLUTIONS Engineering network switches with optional slots for 10GbE fiber uplinks are able to accommodate the growing need for selective high-bandwidth connectivity as a means for maintaining overall network performance. Designed for network interconnection and specialty applications that benefit from maximal pipeline, these solutions bring fiber-optic 10GbE—and unmatched performance—via a variety of connector types to networks for about $2,000 to $6,000 per port, depending on

the type—SR, LR or ER—of connector that’s used (Figure 2).

The level of deployment of optional 10GbE uplinks has grown immensely, confirming that the demand for 10GbE is real and immediate, so stand-alone 10 Gigabit XFP fiber-managed Ethernet switches have found their place in the network as well. And, while 10GBase-T fills an important role for many data center and NAS applications, 10GbE fiber is still unquestionably in demand, and that

demand will continue to evolve and grow.

Using, for example, an 8-port 10GbE Layer 2 managed switch—a core aggregator switch designed to handle heavy traffic workgroups or power users and is capable of reaching up to 160 Gbits/s with a non-blocking switching architecture— can provide that speed and bandwidth over distances of up to 40 kilometers.

The industry will continue to develop Ethernet networking products that incorporate density, efficiency and bandwidth appropriate to varying customer applications, including additional copper and fiber-optic 10GbE, Gigabit and 10/100 Fast Ethernet products.

User demand for 10 Gigabit speed and bandwidth continues to grow, even ahead of budgets, so 10GBase-T solutions will present a lower-cost way to introduce 10GbE where it’s needed most. Switches that deliver 10GbE connectivity over

SMC884M SMC884M Network

Servers

Core Legend 10G Copper 10G Fiber

Figure 2

1 18Untitled-3 January 2008

1/8/08 4:10:35 PM

From the corporate data center, long distance links to other building and subnets are made via 10GbE fiber uplinks from the core aggregator switches. Inside the server room, 10GbE Copper links to servers reduce overall network construction costs without compromising bandwidth.

The Gigabit switch’s 1G connections to internal workstations benefit from the speed gains of bottleneck-freeing 10GbE cross-network and server connections via the uplinks.

SOLUTIONS Engineering

RD

Server

Server

The Harsher the Environment, the More You Need MEN Micro!

RD

Marketing Legend 1G Copper 10G Copper 10G Fiber

Finance Network

Figure 3

D7 Xeon® Blade Server 6U CompactPCI®

Copper 10GbE switches with fiber 10GbE uplinks make more highbandwidth connections without the expense of fiber, while fiber uplinks take care of longer distance runs.

standard copper cabling enable short-run 10GbE connections at roughly half the per-port price of fiber switching—even before considering the savings in cabling.

10GBase-T enables implementation of flexible data centers and short distance networks at a reasonable price—and the ease of installation of Cat6A cabling adds even more to the value side of the equation (Figure 3). Of course, conformance with IEEE802.3an is a critical feature to look for in a 10GBase-T switch—as it provides an IT professional with the assurance that the 10GBase-T switch is fully standards-compliant and interoperable, and will install and operate in any standardsbased Ethernet network. Such a multi-port combination 10GBase-T and 10GbE fiber XFP network switch recently became broadly available: the SMC8724-10BT TigerSwitch 10GbE Stand-alone 24-port 10GbE switch with 20 10GBase-T ports and four XFP-based 10GbE fiber ports for flexible 10 Gigabit connectivity.

10GbE All the Way

While 10GbE fiber uplinks and aggregator switches—and even 10GBase-T—fill important roles for many data center and NAS applications, sometimes relief at the switch is not enough. Switching is central to speed and bandwidth management, but opening the bandwidth further down the line is a priority for many as well. 10GbE network adapters—both fiber and copper adapters for 10GbE connections to servers—that stress performance, thermal management and affordability make the connection down the line, and are rolling out now, with the first of them just re-

cently made available. Several key architectural features that should be included in a good 10GbE Ethernet Adapter include: cut-through architecture for low latency; virtualization of the host interface; and VNIC, for the cleanest, most efficient acceleration of I/O in virtualized operating system deployments, to deliver real performance benefits over a broad range of applications. Thermal management and overall performance must be considered as well. There are now 10GbE Ethernet Adapters for each high-bandwidth application market segment: Network-Attached Storage (NAS) Servers, Storage Area Network (SAN) Arrays, High Performance Cluster Computers, Blade Servers, Video Servers, Application Servers and Web Accelerators. Such adapters are currently becoming available on the market at price ranges starting under $1,000.

10GbE is the answer to today’s pervasive demand for more bandwidth, and deploying it in the most efficient way for a given network can optimize the cost-benefit ratio. High performance is becoming accessible to more companies as IT managers ensure that it’s deployed when and where it can have the greatest impact. Today’s solutions break down the challenges into manageable pieces so that IT managers can leverage the best and fastest technology in an optimal configuration—at a price that enables them to justify the upgrades in more cost-benefit analyses.

SMC Networks Irvine, CA. (800) 762-4968. [www.smc.com].

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■

■ ■ ■

■ ■ ■ ■

2 dual core Xeon® 1.66 GHz ULV processors (4 cores total) cPCI system slot with PCI 64-bit/ 66MHz or PCI-X 64-bit/133MHz 4 GB DDR2 SDRAM with ECC Non-volatile SRAM and FRAM SATA and PATA support for hard disk, CompactFlash and more I/Os include UARTs, USBs, Ethernet 2 XMC or PMC slots Up to 2 GB Ethernet channels Long-term availability: 5 years+

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www.menmicro.com January 2008

19

INDUSTRY INSIGHT

data acquisition

Doing More with Less (Hardware, That Is) By using a system of modular hardware, companies are able to combine the benefits of homegrown flexibility with COTS reliability and support, thus harnessing the full power of flexible, modular I/O. They can select among multiple-channel modules designed for the signal types of interest and configure flexible instrumentation solutions using software.

by B rett Burger National Instruments

d

exploration er your goal eak directly al page, the resource. chnology, and products

T

ake a quick look around; there are one-hit wonders designed to measure a likely no fewer than half a dozen single, real-world phenomenon. A temelectronic devices that all have one perature data recorder did just that, and if thing in common. Three years ago they more measurements needed to be taken, were probably twice the size or had half more equipment, space and money was the capabilities, and in many cases both. required. One of the bigger evolutions Ideally, people want a personal assistant came with the mass adoption of computer to hold everything including a camera, technology. Suddenly, the data acquisition phone, wireless laptop, music player, system was separated into computational clock, address book and more. In lieu of components and measurement hardware that personal assistant, the consumer elec- components. This movement to PC-based panies providing solutions now tronics market is increasing functional- or virtual instrumentation brought great ration into products, technologies and companies. Whether your goal is to research the latest ity by integrating all of these devices of flexibility to the end user, because the lication Engineer, or jump to a company's technical page, the goal of Get Connected is to put you convenience one package, hence the processing and analysis capabilities were ice you require for whatever type into of technology, cell nearly endless with the power of the stanies and productsmultitasking you are searching for. phone.

In pursuit of ultimate flexibility, the dard PC and programmable application instrumentation market is not unlike the software. For data acquisition hardware, consumer electronics market. Companies multifunction devices became available and consultants constantly strive to get for several PC buses including ISA, PCI, the most out of a limited amount of, usu- PCMCIA, PCIe and USB as well as a host ally expensive, measurement equipment. of stand-alone and proprietary protocols.

This drive has led to several evolutions in Data acquisition devices also began to data acquisition. measure several types of signals, includEarlier data acquisition systems, or ing analog and digital, but even with even the more simple data loggers, were multiple signal measurement types, these devices were still fully assembled by vendors, and customers were often left with Get Connected extra channels, unneeded measurement with companies mentioned in this article. www.rtcmagazine.com/getconnected types, or a limited expansion path when

End of Article

20

January 2008 Get Connected with companies mentioned in this article. www.rtcmagazine.com/getconnected

the project grew. And with that, another evolution of the data acquisition system, modular systems, was born.

Modular systems are a great approach for system construction because they allow for a reasonable amount of growth before having to reinvest in additional foundation components. Modular systems and platforms are designed and built by a variety of vendors on several standards, some of which are open such as PXI and VXI, while others are proprietary. The goal of modular I/O is to enable the end user to purchase only the channel count and signals needed and offer the ability to upgrade in the future without having to double the initial investment. Many of the benefits of a modular system are shared by the vendor and the customer. A customer can update, expand, or change a system with the purchase of new modules.

A vendor can more rapidly enhance a data acquisition platform to meet the demand of the customer by adding new modules with new measurements or channel counts to their product lines.

A trend has developed stemming from a single instrument that did everything to having individual components broken out

INDUSTRY Insight

for the user to define and purchase separately at the discretion of the project needs.

This trend has brought together the benefits of commercial off-the-shelf (COTS) quality, reliability and support with those of homegrown customization. As technology advances and the components used in instrumentation have gotten smaller, it has become easier to design smaller components for data acquisition systems. Modules that started as trays fitting into large card cages have evolved into smaller modules slightly larger than a deck of playing cards. In the ever-shrinking trend of hardware and modules, size has not sacrificed channel count, as some of these smaller modules offer more than 30 channels and may be placed in different chassis types for different configurations for various deployment options (Figure 1).

One-channel modules may or may not be an economical solution, but either way, the disaggregated module movement is ending. This begs the question “what is next?� The answer can be found by looking at some higher-level benefits of a modular platform. Modular systems have reduced the number of systems needed and components in a test department’s equipment library by using exchangeable modules in a single chassis or carrier.

One of the remaining problems is that channel count and signal type are only two characteristics that can change. Selfcontained measurement modules solve the problem of changing channel count and signal type, but the market demands more flexibility.

The next evolution of data acquisition systems is to exchange not only modules, but chassis for deployment as well. The test process, depending on the device, has many stages including design validation, controlled environment testing, subsystem component tests, hardware simulation tests, prototype tests, end-of-line manufacturing test and more. By creating a data acquisition system comprised of interchangeable modules and deployment options, test designers can further reduce their hardware needs and thus expenditures, storage space, vendor contacts and toolchain training for employees.

To fully harness the power of modular I/O, it is important to maximize reusability. Just as there are different modules

Figure 1

The C Series family of hardware is composed of over 40 modules and multiple deployment options. Shown here: desktop chassis, industrial computer (CompactRIO) and USB single-module carrier.

for different measurements, the next evolution of modular data acquisition systems will have different deployment options for the same set of modules. Deployments will vary between industries, but will include options such as size, portability, PC-connectivity, ability to run in a standalone mode, ruggedness, reliability and so on. And, as with modules, no vendor will cover every possible use-case, but a family of modular, flexible hardware should be able cover a wide array of the aforementioned deployments.

To better illustrate this, consider a scenario where a fictional company deploys a single-vendor flexible deployment hardware platform.

Assume this company is a consultantfocused engineering house specializing in rotating equipment monitoring and maintenance in the machine condition monitoring (MCM) industry. This company uses accelerometers for vibration measurements. Accelerometer measurements are on the higher end of sensor measurements due to the high sample rate, resolution and bandwidth required. In addition, such integrated electronic piezo-electric (IEPE) sensors require current excitation to power the sensor. Anti-alias filters are a benefit to remove any traces of highfrequency noise in the system, and due to the speed of acquisition and nature of phenomena, simultaneous sampling

ADCs are preferred to ensure signals are in phase. Using a modular platform, all of this signal conditioning and data acquisition circuitry must fit into one module.

Measurements performed by an MCM specialist are often from proximity sensors for shaft alignment, tachometers for shaft rotational speed, power load by the motors, and accelerometers for vibration analysis on bearing housings. These measurements are performed in different deployments. One application is the small, low-channel-count, portable unit that a consultant travels with for spot-checks on systems. These spot-checks can be done routinely or when a noise is heard by an operator and called in as a problem. Portable deployments require portable display, storage, reporting and easy setup.

More complicated deployments involve a larger channel count for complete machine testing and mixed sensor types, since a complete machine check-up will have tachometers, proximity probes and accelerometers. This larger-scale monitoring system may have bigger storage and processing requirements due to the vast amounts of data involved. The system needs to be moveable, but not as portable as the spot-check system. With the temporary install location often in an industrial environment, the equipment must also be rugged. The final level of machine maintenance that this company offers is January 2008

21

INDUSTRY Insight

the permanently mounted monitoring system. These are online systems installed on rotating equipment to constantly monitor the health of the system and, when the limits are exceeded, notify managers of necessary repairs, or sound alarms or initiate emergency shutdown procedures in hazardous situations.

The company in this scenario is comprised of engineers and service technicians with significant industry experience in machine condition monitoring, but limited understanding of hardware design. In today’s market, the company must purchase several devices: a one-box solution originally designed a decade ago and is slightly large for full-system monitoring, a newer PC-based solution for the portable system that runs off of a laptop (Figure 2), and a more expensive, ruggedized brick-style system for the permanently mounted system. With these choices, the company must buy, learn and maintain a lot of different equipment, or try to find one vertical vendor that makes all three types of systems.

But even with one vendor there may be a

Figure 2

The single module carrier connects to a PC over USB for a low-channel-count, portable solution that can connect to a laptop for field applications. Individual modules can be easily swapped out of the carrier.

concession in quality or performance for a one-vendor solution. The other, preferable choice is to design and build their own systems. This ensures that the specs needed are met exactly and all functions are available. However, this company has more technical knowledge in collecting, reading and interpreting the results than hardware design.

The solution is to use a family of hardware with modular I/O and flexible deployment such as the C Series family of hardware from National Instruments. This collection of hardware offers more than 40 measurement modules that are a little larger than a deck of playing cards. These modules can be used in any one of several different chassis for multiple deployment options. In our example, an accelerometer module could be used in the singlemodule carrier with a rugged laptop for a portable vibration measurement system. For the full system monitoring, the same module could be inserted into an 8-slot chassis along with other modules for proximity probes and tachometers.

For larger machines, multiple chassis can be linked together and synchronized for in-phase measurements.

Finally, the same set of modules can be inserted into an industrial computer chassis for a permanently mounted monitoring and alarming system. The CompactRIO chassis, for example, offers either four or eight slots and has a builtin storage and processing capability in an extremely rugged housing, and operates in environments ranging from -40° to 70°C and up to 50g shock.

Hardware is just half of the equation; software must still be considered.

Functions such as FFT, order analysis, orbital analysis and waterfall plots are needed for a complete MCM system.

This analysis and experience is where the consulting company’s expertise lies, and using software from the same vendor, NI LabVIEW, a company can write and reuse analysis code on all three application deployment platforms. With this one-vendor flexible solution, this consulting house can better manage the training and hardware needed for complete customer service. Should the company decide to resell the systems, the COTS benefits kick in again, because of the manufacturing resources of the selected big name vendor.

National Instruments Austin, TX. (512) 683-9300. [www.ni.com].

1 22Untitled-6 January 2008

1/8/08 4:17:39 PM

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INDUSTRY INSIGHT

data acquisition

Data Acquisition: Harnessing Small Modules with Flexible I/O Techniques used for effective implementation of remotely deployed small form-factor data acquisition modules are increasingly looking to wireless sensor networks due to their dynamic reconfigurability, robustness and ease of deployment of small form-factor sensor nodes.

by S cott Hames GE Fanuc

S

mall form-factor data acquisition devices can be thought of as the sharp end of the stick in a system of remotely deployed sensors. Often the reason they are small form-factors (SFF) is because the details of the deployment (size, weight, cost, etc.) prevent the use of COTS form-factors such as PMC, AMC, etc. Regardless, remotely deployed sensors of any form-factor are in fact data producers for a centralized data consumer process. The fact that they are not connected to their hosts by a data bus requires them to use unconventional I/O methods.

There are various objectives of remote sensor deployment. Among them are the need to make measurements at remote locations, to simultaneously measure a variable in multiple widespread locations, and the need to measure a variable where the sensor will be lost or destroyed in a relatively short time. Additionally, remote deployments often carry with them restrictive space, weight and power requirements. Air-launched sonobuoys are possibly the ultimate example of remote deployment. Because they operate on batteries, power consumption must be frugal.

24

January 2008

Airborne equipment performs signal processing, target tracking, recording, etc.

Deployed sonobuoys transmit sonar returns.

99 channels 136 - 174MHz

Figure 1

Legacy wireless sensor architecture.

They are deployed once and are likely to never be recovered, so they must be cheap. Additionally, sonobuoys are usually deployed in significant numbers (99 channels are theoretically available) from patrol aircraft or helicopters, so size and weight must be kept low.

With the special requirements of remote sensing in mind, SFF DAQ modules are deployed in one of three ways: fixed sensors with a hardwired connection, fixed sensors with a wireless connection and mobile sensors with a wireless connection.

Fixed/Hardwired: USB

Fixed sensor arrays are often encountered in industrial process control applications, where a number of sensors transmit data back to a central control system.

Early systems used analog parameters, such as electric current in a control loop, to represent physical conditions such as flow rates, pressures, or temperatures.

Modern systems represent the process variables as digital data and communicate with the controller using commodity communication links such as USB. The rapid acceptance of USB 2.0 in industrial control provides an example of fixed sensors and hardwired connections.

Over the last few years, USB has become a ubiquitous mechanism for connecting computers and various I/O devices. It is readily available on virtually all styles of PCs, and also on most single board computers and stand-alone instrumentation, regardless of the host OS. USB also offers the user a combination of low price, good performance, reliability and “plug and play� installation. Because differential signaling is used, USB has strong resistance to noise typically encountered in factory environments.

INDUSTRY Insight

The easy installation capabilities of USB also allow industrial sensor systems to be quickly modified. Hot swap/hot plug capability means that in many cases USB modules can be unplugged and reinstalled in new locations without interrupting system operations.

USB 2.0 offers this easy connectivity for up to 127 devices, enough to monitor several complex industrial processes from a single PC. And with commercially available USB hubs and extenders, the reach of USB connections can be extended to well over 100 meters. One of the biggest benefits of USB for remote deployments is the fact that the same cable that provides communication also provides the sensor power. Although the total power available from a USB host is low (mandated at 0.5A @ 5V), many commercially available hubs provide additional power to USB devices.

signal processing and software defined radio technology now allow use of modern waveforms. Typical legacy airborne antisubmarine warfare (ASW) systems support 8 to 32 concurrent sonobuoy receiver channels selected from any of 99 channels in the VHF band 136 to 174 MHz.

Mobile Wireless

Mobile Ad-hoc Networks (MANETs) represent one of the most challenging applications of small form-factor data acquisition modules. However, creative implementation of MANETs is yielding some very efficient ways to collect data from

Fixed Wireless

Fixed wireless connections are used in applications where physically connecting the sensor nodes is inconvenient, undesirable, or impossible. In factory applications similar to the fixed and hardwired example, a wireless architecture will enable rapid deployment of a new sensor network with little or no additional infrastructure.

An excellent example of a legacy “fixed” (to use a term loosely) wireless SFF DAQ system is the sonobuoy. These are typically either active or passive airlaunched sensors that are used in various marine applications from submarine detection to sea state monitoring, to animal tracking. Each sonobuoy contains its own radio transmitter, which relays data back to a receiver located in a patrol aircraft or helicopter. The buoys themselves do little or no processing, merely relaying data back to a host system. Each sonobuoy typically transmits on a preset carrier frequency, and the host is responsible for receiving all the deployed channels, or at least those of interest.

Figure 1 shows a typical airborne acoustic processing system. The basic signal acquisition system architecture has changed little since the Second World War. This type of signal distribution was originally based on analog FM radio technology, but advances in digital

26

January 2008

Figure 2

Some of the form-factors specified in the JTRS HMS inventory.

remote, sometimes dangerous, environments. Ad-hoc wireless sensor networks consist of large numbers of small, cheap and often single-use devices, each capable of limited computation, wireless communication and sensing. The actual sensor nodes are deployed as close to the signals of interest as possible, and ideally the sensors are actually mobile. Rather than routing signals of interest directly to a centralized location for sampling and processing, information moves among the nodes en route to its destination.

Wireless sensor networking technologies are heavily employed in the U.S. DoD JTRS HMS specification, which defines radio equipment characteristics for a wide range of applications, and re-defines the problem as wireless tactical networking.

The JTRS HMS Requirement

The U.S. Department of Defense Joint Tactical Radio System (JTRS) has placed new space, weight and power chal-

lenges on the handheld, man pack and small form fit (HMS) radios. These radios are intended for deployment in a wide variety of systems and platforms such as unattended ground sensors, UAVs, robotic vehicles, and on the soldiers themselves (Figure 2).

The objectives of the JTRS HMS include networked communications among various levels of command and the ability to support technology insertion upgrades while maintaining interoperability with existing equipment. With this in mind, wireless tactical networking is one of the most critical capabilities the JTRS program will deliver. Like commercial wireless sensor networks, wireless tactical network nodes (soldiers) often move and the bandwidth of the links can be very limited. MANET protocols mentioned above are designed to handle these wireless environments. The MANET protocols will be used in conjunction with new JTRS networking waveforms, to permit soldiers in the field to connect to the DoD’s Global Information Grid. Software Defined Radio technologies are being employed to meet the performance objectives within the aggressive new space, weight and power limits.

WSNs (and WTNs) have their roots in packet radio systems. Military packet radio networks from their very beginning developed hardware, software and protocols that could adapt to the changing topologies and environments that were expected on a battlefield. Growing out of the University of Hawaii’s ALOHANET, the DARPA-sponsored Packet Radio Network (PRNET) project extended the single-hop packet radio into a multi-hop packet radio network. Unlike most amateur packet radio networks, the PRNET project designed and tested protocols in environments where the nodes were expected to be mounted on mobile platforms, such as trucks. As a result, the protocols had to adapt automatically to changes in topology, although routes were expected to remain stable for at least a few minutes.

Mobility of the sensor nodes increases the complexity of the networking problem considerably. In contrast to traditional wired networks, routing in a WSN is both highly dynamic and ad hoc. The idea of ad

INDUSTRY Insight

Cell Phones

P2P Over Internet

MANET Mesh

Alert

Content Subscriber

Sensor Network Relay Broker Broker Node w/ Event Correlation Cluster Head (Aggregator)

Figure 3

A ZigBee network can incorporate a variety of topologies.

hoc networking is sometimes also called “infrastructureless” networking, since the mobile nodes in the network dynamically establish routing among themselves to form their own network on the fly. For example, after the initial deployment, sensors may fail due to damage or battery depletion. Also, mobile radios or sensors are likely to experience changes in their position, available energy and task details.

Changes in the environment can dramatically affect radio propagation, causing frequent network topology changes and network partitions.

Wireless sensor networks often deploy large numbers of sensors. Although they don’t require high bandwidth, they usually require low latency. And because the sensors themselves are usually battery powered, minimal power consumption is a must. These requirements are similar to those imposed by the JTRS HMS radio specifications, which are heavily based on networked communications. Because technologies such as Bluetooth and ZigBee are aimed at providing short range wireless ad-hoc networking capability to low-cost, battery-powered devices, techniques and algorithms developed for commercial markets could well be adapted for military use. For commercial applications, ZigBee (IEEE 802.15.4) in particular has great potential in the area of wireless sensor networks (Figure 3).

ZigBee Wireless Networks

ZigBee’s general characteristics include use of dual PHY (2.4 GHz and 868/915 MHz) with Data rates of 250

Kbits/s (@ 2.4 GHz), 40 Kbits/s (@ 915 MHz) and 20 Kbits/s (@ 868 MHz). The protocol is optimized for low duty cycle applications (<0.1%). CSMA-CA channel access yields high throughput and low latency for low duty cycle devices like sensors and controls. It also provides for an optional guaranteed time slot for applications requiring low latency as well as for low power usage with battery life ranging from multi-month to years.

ZigBee allows for multiple topologies including star, peer-to-peer and mesh, and is a full handshake protocol for transfer reliability with a typical range of 50m (5-500m based on environment).

ZigBee uses spread-spectrum technologies to avoid multi-path fading and increase robustness. This approach allows for improved signal immunity in the presence of radio interference.

The IEEE 802.15.4 standard defines two PHYs representing three licensefree frequency bands that include sixteen channels at 2.4 GHz, ten channels at 902 to 928 MHz, and one channel at 868 to 870 MHz. The maximum data rates for each band are 250 Kbits/s, 40 Kbits/s and 20 Kbits/s, respectively. The 2.4 GHz band operates worldwide while the sub1 GHz band operates in North America, Europe and Australia/New Zealand. The IEEE standard is intended to conform to established regulations in Europe, Japan, Canada and the United States.

GE Fanuc Charlottesville, VA. [www.gefanuc.com].

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SYSTEM INTEGRATION

ip for programmable logic

Enabling the Use of FPGAs with Optimized IP The combination of FPGA-optimized IP with a domain-specific development environment enables the non-traditional FPGA designer to realize the full benefits an FPGA has to offer.

by T om Hill Xilinx

d

exploration er your goal eak directly al page, the resource. chnology, and products

T

he benefits of an FPGA are clear: Hardware they can deliver a significant perAccelerated Custom Local formance boost for applications that Functions Memory benefit from parallelism, or dramatic cost savings through consolidation of the funcMicroBlaze PowerPC tions of multiple chips onto a single device. Often, these benefits are perceived to External Memory Interrupt be out of reach to developers whose priController Controller mary design experience is with DSPs or DMA Timer/PWM general-purpose processors.

Ethernet MAC PC/SP1 Intellectual property, tightly intepanies providing solutions now grated into domain-specific design flows, UART PCI ration into products, technologies and companies. Whether your goal is to research the latest enables non-traditional FPGA designers to lication Engineer, or jump to a company's technical page, the goal of Get Connected is to putCntlr you CAN/MOST Peripheral quickly create hardware sysice you require for whatever type ofsophisticated technology, using FPGAs. Unlike the processor, ies and productstems you are searching for.

Custom IO the FPGA does not come pre-equipped Peripherals with a hardware architecture, so rather than simply programming the device, the Figure 1 FPGA-based Embedded developer must also create the device. This System. implies a basic knowledge of hardware architectures for complex functions and in- System Overview terface standards. If these operations are FPGAs allow users to preserve the not designed to efficiently use the FPGA easy-to-use programming model of a hardware resources, then the performance processor while optimizing hardware and cost benefits are compromised. for a specific application. The fixed architecture of a processor removes a degree of freedom in the development Get Connected process that facilitates rapid developwith companies mentioned in this article. www.rtcmagazine.com/getconnected ment of an application. Performance

End of Article

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January 2008 Get Connected with companies mentioned in this article. www.rtcmagazine.com/getconnected

issues for hardware relying on standard processors tend to be addressed through additional devices. Common solutions typically involve using multiple processors for parallelism or an FPGA coprocessor to accelerate performancecritical functions. FPGAs, however, are uniquely positioned to provide a singlechip solution that can be tailored to an application’s specific requirements.

Implementing an embedded system on an FPGA lets developers customize the system to include multiple hard or soft core processors, select a unique set of peripherals and include hardware accelerated custom functions implemented on the FPGA fabric. This flexibility allows performance issues to be addressed while minimizing cost and power. Figure 1 provides a block diagram of a typical FPGAbased embedded system.

Can such a system be created by a traditional processor developer with limited FPGA design expertise? Will the implementation of this system use the available FPGA resources sufficiently for production hardware? The answer to both these questions is “yes,” through the use of FPGA-optimized IP

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SYSTEM Integration

275

Spartan - 3A DSP 250 250

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Symmetric 69 tap decimate by 6

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FIR Specification

Figure 2

FIR Filter Performance Comparison between Spartan-3A DSP and Spartan3A.

integrated into domain-specific design flows now available for embedded and DSP development.

FPGA-Optimized IP

Device-optimized IP reduces the barrier to adoption of FPGAs for non-traditional developers of production systems.

Vendor-independent IP is an understandable choice when the FPGA is being used to prototype an ASIC. This retargetability, however, comes at a cost in silicon efficiency. When the FPGA is included in the production hardware, the quality of results will have a direct effect on the cost and performance of the overall system. In these situations, IP that has been specifically optimized for the FPGA is a preferable option.

FPGAs have grown in recent years into sophisticated devices that provide a variety of specialized hardware resources. These enhancements to the original “sea of gates” architecture are what allow these devices to achieve their compelling performance, cost and power metrics. For example, today’s largest FPGAs include, in addition to over 51,000 slices of configurable logic, up to 640 dedicated DSP blocks that can

30

January 2008

be programmed to perform a variety of operations, 10 Mbytes of block RAM, hardened embedded processors and dedicated interconnect IP such as PCI Express and Ethernet.

RTL synthesis, in the hands of seasoned FPGA design experts, is a proven flow for developing hardware-efficient implementations. This flow, however, is not always viable for developers with programming backgrounds. Production quality results are achievable without RTL design skills using IP that has been optimized for the specific FPGA. IP provided by FPGA vendors is painstakingly optimized by in-house design experts for each supported technology. For example, an IP core optimized for a Xilinx Spartan-3A device would have to be re-optimized for a Spartan-3A DSP device to take advantage of new features such as the DSP48A slice. Figure 2 shows the effects of this type of optimization by comparing the results of the Xilinx FIR Compiler IP generator between the Spartan-3A and Spartan-3A DSP device families. Developing an implementation that targets these slices increases the filter performance by 73% while reducing device utilization.

Figure 3

Wizard-based Embedded System Development.

Creating the Embedded System

The most natural migration from processor-based hardware to an FPGA is to develop an embedded system that is sufficiently optimized to meet the system performance requirements. This preserves the programming model for application development while allowing the architecture customization to address performance issues.

Easy-to-use wizard-based flows, such as Xilinx Base System Builder (Figure 3), are available from FPGA vendors for creating the initial embedded hardware. A series of forms allows a user to configure an embedded processor, connect it to the processor bus and select a unique set of peripherals in a few minutes.

Once the initial embedded system has been created it can be further optimized using an embedded hardware development environment, provided by the FPGA vendors (Figure 4), that provides a bus-oriented view of the system along with a catalog of additional embedded IP and automatic generation of hardware and software driver files.

IP integrated into a processor-oriented development environment brings this type of architecture flexibility within reach of designers with varied backgrounds. Fully exploiting the advantages

SYSTEM Integration

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Figure 4

FPGA Embedded Development Environment showing IP and Buses.

data_out 1 din

data_in

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2 vin

a b

3 start

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info_generator

3 info 5 err_cnt 4 fail

Fanless AMD LX-800 Universal Controller

rrfd RS Decoder

Figure 5

Simulink-based FPGA Design.

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Spartan 3-DSP / Virtex-5 Platform Studio

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Embedded Interface Generation from System Generator.

of an FPGA-based embedded system, however, requires the creation of FPGA accelerated custom functions for use by the embedded system.

Turbo-Charging the Embedded System

Developing an embedded system on an FPGA allows performance-critical functions to be “turbocharged” through hardware acceleration on the FPGA fabric. Profiling the application code allows identification of “hot

spots” that diminish the performance of the entire system. Calls to functions executing on the processor can then be replaced with calls to functions that execute on a dedicated hardware accelerator implemented in the FPGA fabric.

These custom instructions can dramatically improve the performance of the entire system.

Creating efficient hardware accelerators requires optimal use of the available FPGA resources. Traditional processor programmers often don’t have

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Untitled-1 1

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31

10/18/07 10:50:24 AM

SYSTEM Integration

the background to accomplish this type of low-level FPGA design. Automated â&#x20AC;&#x153;C-to-gatesâ&#x20AC;? flows have emerged as a possible solution. These flows are software centric and allow performance bottlenecks, identified through profiling, to be mapped to the FPGA fabric using a pushbutton approach. Modest performance gains are achievable but the hardware results tend to be more suitable for prototyping than for production hardware.

An alternative approach would be to use a domain-specific development environment with FPGA-optimized IP. Such environments exist today for DSP applications that enable the use of The Mathworks DSP-friendly Simulink / Matlab modeling environments for FPGA development (Figure 5). Vendor-optimized libraries are provided for use within Simulink that include up to 100 DSP building blocks. Creating the design within Simulink allows these blocks to be abstractly connected and verified within the context of a DSP simulation.

Integration now exists to allow DSP development environments to automatically convert designs into custom peripherals for a corresponding embedded development environment.

Integration includes the ability to automatically generate the hardware interface and software driver files and can often save weeks of development time (Figure 6).

It is the combination of FPGA-optimized IP tightly integrated into a domain-specific development environment that enables developers with programming backgrounds to leverage the flexibility of an FPGA-based hardware system for their applications. These development environments are able to abstract away low-level implementation details of the interconnects and present the IP as abstract system building blocks in an appropriate context.

Embedded development environments present a bus-centric view of the systemâ&#x20AC;&#x201D;including masters, slaves and peripheralsâ&#x20AC;&#x201D;which makes sense for em-

bedded development, while DSP development environments present a dataflow view of the system that includes fixedpoint bit growth and key DSP operations such as filtering or transforms, which is intuitive for DSP development. Integration between these two environments makes including a hardware-accelerated customer function for DSP a straightforward process. Because the IP supporting these environments is optimized for the target FPGA, production quality results are achievable, and the performance, cost and power benefits of the FPGA are fully realizable.

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Part of

SYSTEM INTEGRATION

IP for Programmable Logic

Software Developers Empowered by the FPGA Revolution The concept of self-integration involves a form of design automation, enabled by FPGAs, where a software engineer can quickly create custom functioning hardware with supporting OS and driver software.

by E ric Schneider Eridon

d

exploration er your goal eak directly al page, the resource. chnology, and products

“P

rogrammable” hardware lets duction. Benefits include inherent design the “software design” drive flexibility, improved time-to-market and and automate aspects of risk reduction. Thus you can jumpstart “hardware design.” Think of an FPGA application coding using self-integrating chip as “liquid silicon” in which digital subsystems—subsystems where software logic is downloaded to create processors, (drivers) and hardware modules just snap peripherals, buses and glue logic. Since together like Legos (Figure 1). its contents—much of your hardware deYou build things more quickly when sign—are fashioned not from solder but pieces fit together. A software engineer from keystrokes, it is possible to drive and can go from concept to working hardpanies providing solutions now automate the traditional hardware design ware using tools that leverage an FPGA, ration into products, technologies and companies. Whether your goal is to research the latest from a software-centric development en- such as Eridon’s UnifiedLogic Developlication Engineer, or jump to a company's technical page, the goal of Get Connected is to put you vironment (IDE). ment Platform. We begin with the central ice you require for whatever type of technology, In searching simple for. terms this means that as tool in a software developer’s world, the ies and products you are an initial step, your software engineer Integrated Development Environment specifies the various required hardware (IDE). Here there are three windows subsystems and through automation has (Figure 2): one in which you describe much of the hardware design and sup- your product’s hardware as well as its porting software (RTOS and drivers) put software structure, an edit window in in place. In fact, the software engineer which to compose the application, and can even rapidly prototype the described a build/debug window through which system and begin programming on real your product comes to life on real hardhardware, which will essentially be the ware. In broad strokes, you “right-click” same hardware you will later put into pro- in the hardware description window, add various subsystem modules such as USB, Ethernet, SPI buses, video and so Get Connected on, compose some software, and click with companies mentioned in this article. www.rtcmagazine.com/getconnected “run” to begin debugging.

End of Article

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January 2008 Get Connected with companies mentioned in this article. www.rtcmagazine.com/getconnected

Figure 1

Snapping together a custom embedded system out of essentially off-the-shelf reference designs is by itself unprecedented, and also yields additional benefits such as off-loading timingcritical tasks to hardware.

This is not only possible with FPGAs, but tools now make it easy and automated.

SYSTEM Integration

This might sound like RTOS configuration combined with a traditional software development environment, and it is. But now that your PC can also generate much of the hardware design, the IDE goes further to cross the hardware-software divide. Essentially, put an FPGA on the end of a USB cable, and your IDE can “link” both the software into an executable image as well as “synthesize” the corresponding hardware into gate-level logic.

In other words, say you add a USB device to your design. You not only get the drivers and operating system by which to control it, but also the hardware logic

custom hardware in your hands. Because both the hardware and software sides are now programmable from the same IDE, tools that are able to see both sides can automate and manage many of the previously tedious details. As useful as it is that you can integrate hardware logic and software subsystems on your PC, the trick is to get to real hardware.

Now we can also introduce little add-on modules that plug into a devel-

To go from product concept to an application-ready hardware prototype, the software engineer simply enters the required hardware subsystems and attaches what are often completely off-the-shelf modules to an FPGA-based development board. Of course, it is a sophisticated framework (Figure 3) that lets the IDE automate much of the integration—integration both within a given subsystem of its hardware and software components, as

RTOS Services RTOS, drivers, and application code UnifiedLogic IDE

System Specification

IDE

Hardware

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H/w+s/w Build & Debug

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Figure 2

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Hardware and Software in One

Subsystem Modules

PC USB

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Add-On Modules

A software engineer can use a single tool to both automatically configure an operating system and automatically integrate the hardware design, now that software and custom hardware can be built using a PC (no solder required).

placed in an FPGA to make it a physical reality. Interestingly, downloading during development thus involves both executable code and gate-level level logic. You might be thinking, “How does the IDE download a serial port connector or an LCD screen?” But an FPGA uniquely opens up just such possibilities.

Though a software engineer can write code and moments later really run it, we all know this is a stark contrast to placing chips and melting solder to make custom hardware. Hardware takes months of work in design, layout, fabrication, parts acquisition, assembly and the iterations to make it actually work, not to mention communicating the relevant details such as memory map and interrupt structure to the software team. An FPGA dramatically changes this paradigm allowing you to rapidly put

H/W

Software Driver

Hardware Ref Design

API Documentation

Schematics Bill of Materials FPGA gate logic

Figure 3

Self-integration requires a new level in defining it—UnifiedLogic defines a subsystem as a software driver, gate-level hardware logic (IP) that handles interfacing and off-loading of timing-critical tasks, and schematics and a BOM (for the associated circuitry that gets attached to the FPGA). Each provided in a “unified” form ready to integrate with others subsystems.

opment board and connect to an FPGA’s pins. These modules typically provide the translation from the FPGA’s digital insides to the physical world. For example, one module might contain the minimal circuit to convert PWM audio into some watts to which you can attach a speaker, or a PHY to convert Ethernet packets from binary to the signals that run down a CAT5 cable. Thus, when you are in the IDE and right-click to add a subsystem module, envision the library as also including small boards (or at least schematics) that get you from the software driver to perhaps an LCD screen, or a motor.

well as integration of all the subsystems as a whole.

Has a PC’s “Plug ’n Play” of peripherals arrived for embedded systems?

Plug ’n Play shares the goal of assembling a custom system from modules under a framework in which everything self-integrates, freeing you to focus on tasks where you really add value—like writing the application. However, as required for an embedded design, an FPGA avoids the cost and inefficiencies of buses such as PCI, yielding practical cost-effective designs that can be put into production—designs in which all the digital logic, even including a CPU, January 2008

35

SYSTEM Integration

are consolidated into a single chip surrounded by a minimum of additional hardware to bridge from the digital to the physical world. Thus, if your peripheral is just an LED, you will only need a single line from the FPGA. Let’s look a little closer at how a subsystem gets from a software driver, to its gate-level logic in the FPGA, and finally to some external circuitry and connectors.

Interconnect Flexibility

What is uniquely possible with an FPGA, as opposed to a hardwired chip such as a microcontroller, is that digital logic (gates) can be assembled inside the FPGA and the corresponding signals brought out to arbitrary pins. Thus, if you want your audio on Pin 1 or Pin 10, it is simply a matter of the IDE making the appropriate adjustments in the hardware and software. Of course, a software en-

Dissolve away the unneeded connectors and traces from your prototype and what is left is essentially the same circuit that would be put into production.

Figure 4

36

Since FPGAs can assign their pins arbitrarily, it is possible to connect circuitry to an FPGA and then subsequently program the FPGA to control the circuitry. This ability is leveraged by Eridon’s uCard modules to enable rapid prototyping of a mix of peripherals that also reflect a design suitable for production.

January 2008

gineer doesn’t care what pin it is on, just that there is a jack to plug in a speaker.

The challenge here is to connect a variety of arbitrary modules to an FPGA on a development board, so you prototype what you really want for your product. With a subsystem implemented in both internal FPGA logic and external circuitry, it will require some number of FPGA pins—perhaps few, perhaps many—to interface the two sides, avoiding a large inappropriate bus. Though it may seem like a detail, it is a development board’s dilemma as to provide either lots of lines on one large connector or lots of lines via small but potentially inadequate connectors. One size just does not fit all in embedded systems.

Through the use of an “IN” and “OUT” connector, uCard add-on modules daisy-chain together, with each peeling off the number of lines its circuitry requires (IN) and passing along the unused lines to the next module in the chain (OUT).

Thus, a large connector on the development board makes as many FPGA lines as needed to a chain of attached modules (Figure 4). This allows your prototype to have a good number of diverse subsystems (so long as there are enough total lines to drive them all). Even a software engineer can simply snap everything together and closely, if not exactly, create a prototype of a desired product.

ID chips are included on each uCard so that the IDE (through the development board) can auto-detect your configuration and populate the hardware tree.

This includes taking care of pin assignments—the IDE determines what subsystem is connected to what FPGA pins and automatically connects the proper gate-level logic to the pins, plumbing everything back through to the software drivers. Tedious and error-prone tasks are eliminated.

The use of an FPGA and off-theshelf modules that encompass both hardware and software drivers can dramatically accelerate product design and make it initially a much more software-centric process. But don’t let the hardware engineers go golfing yet. There is still plenty to do—either initially by adding any circuitry not available off-the-shelf (your product’s “secret sauce”) or taking the

SYSTEM Integration

design—what amounts to a collection of snapped together reference designs—to production by condensing and optimizing it into a single board (Figure 4). For example, your hardware engineer may select a smaller, more cost-effective FPGA than was used on the development board, as well as consolidate I2C and SPI buses to reduce total pin count.

Benefits for the Software Engineer

There are other benefits too. For the software engineer, real-time computing is easier to achieve using an FPGA, even without any understanding of the FPGA itself. This comes from the fact that the off-the-shelf subsystem modules can implement time-critical tasks and buffering in the FPGA’s hardware. Everything that needs it can have hardware acceleration, which is not so easy if using a system-ona-chip. For example, the complex blending of audio channels into a serial stream for transfer can be done in hardware; tracking and precise motor control can be done in hardware, as can the transfer of video to and from memory. Of course, this acceleration was possible before programmable hardware came along, but it previously required intense hardware engineering.

Now, with subsystems designed from the ground up that leverage programmable hardware and that self-integrate, it is easier for the software engineer to achieve real-time performance without waiting for complicated hardware development.

Supporting software development offers a great example of a subsystem module that makes good use of real-time hardware acceleration, a module used on both development boards and final products. Consider the problem of how to print a floating-point number from an interrupt handler. If you try to convert it to ASCII (printf) and send the characters out a serial port you will likely interfere with the realtime nature of your system. Further, if you were already in the middle of printing a number in a different context, the two outputs could get mangled. These problems are all addressed by “printing” based on using a simple assignment (typically two instructions) to move a variable to a hardware accelerated subsystem mapped at a specific address.

Prints from different threads and interrupts each use their own unique addresses, which get translated by the hardware into channel IDs. The subsystem combines the binary value, formatting and channel information and writes it to a FIFO. On the other side of the FIFO is either a standard serial port or another low-cost interface. Prints are transferred to the IDE running on your PC where the binary-to-ASCII conversation is done and displayed in appropriate windows (by channel ID). Further, communication is bidirectional. Thus you can type into a window in the IDE (PC) and get and test for these keystrokes inside your application (product). This development subsystem “module” is also used for file transfers, allowing you to drag-and-drop files from your PC into a product’s flash.

One might think there is a lot of setup involved to use such a subsystem, but because the IDE sits on top managing the operating system, drivers and gate-level logic, it can automate all the plumbing. A software engineer just adds the subsystem to the hardware project and begins using it.

The embedded space has traditionally been hampered by the effort required to create and adjust designs, realizing that architectures either tend to be rigid, or if flexible, they are costly and inefficient.

A “unified” modular, self-integrating platform avoids many of the problems faced when using hardware, software and tools from disparate sources, and opens the door to automation and the effective use of programmable hardware by the software engineer. This leads to a paradigm shift where instead of having a hardware engineer search for suitable hardwired chips to adapt to a product’s needs, you can instead “create” the specific custom gate-level logic you need, and focus on one type of chip—the FPGA—for the most part, regardless of how your needs evolve.

Accelerate your FPGA application development

Impulse C™

provides a fast path between your software and hardware development tools and methods.

Iteratively optimize your C code for higher performance using interactive tools. The Impulse C compiler generates hardware outputs ready for use with popular FPGA devices and platforms.

Impulse tools are fully compatible with FPGA development tools, and with popular C-language compilers and debuggers for algorithm verification.

Applications Include UÊ 6 `i Ê«À ViÃà } UÊ } Ì> Êà } > Ê«À ViÃà } UÊ Ì>ÀÞÊ> `ÊÃiVÕÀ ÌÞ UÊ i` V> Ê >} } UÊ ÕÌ Ì ÛiÊ> `Ê>iÀ ë>Vi UÊ } Ê«iÀv À > ViÊV «ÕÌ }

Contact us to learn more

www.ImpulseC.com 425-605-9543 x101

Eridon Wayzata, MN. (612) 802-6178. [www.eridon.com].

January 2008

37

FeaturedProducts GHz Digital Receiver PMC/XMC Module Offers 2- or 4-Channel Operation

A rugged ADC PMC/XMC module designed for deployment in harsh environments offers both two- and fourchannel operation with sampling frequencies of 1.5 GHz (four channel) or 3 GHz (two channel) for Software Defined Radio (SDR) applications such as spectrum monitoring, signal intelligence, tactical communications and radar. The ICS-8551from GE Fanuc Intelligent Platforms combines high-performance ADC and FPGA resources and allows VHF and UHF signals to be digitized and processed directly on the module. Algorithms such as digital down conversion, FFT and filtering can be developed to execute in the onboard Xilinx Virtex-4 FPGA (XC4VFX60 or XC4VFX100), using the included Hardware Development Kit (HDK).

The ICS-8551 provides up to eight lanes of high-speed serial I/O, at rates up to 3.125 Gbytes/s, for communication with XMC-equipped carrier cards such as the GE Fanuc Intelligent Platforms V4DSP front end signal processor. The 64/66 PCI interface provides sustained data rates in excess of 400 Mbytes/s, while the Pn4 user I/O port allows the user to define direct point-to-point connections to the FPGA, eliminating interrupt latencies. The latter two interfaces may be used for applications in which the XMC interface cannot be used.

The ICS-8551includes both a default logic core and a digital downconverter (DDC) IP core. The default logic core provides a basis for customers to program their own functionality. It includes an A/D interface and data buffering to the high-speed serial outputs and to the PCI bus, via FIFO buffers. The DDC core enables a band-limited signal at a given (programmable) intermediate frequency to be shifted in frequency to base band, then filtered and decimated prior to output. Output options include the high-speed serial outputs or the PCI bus. Other features including protocol cores will be added to the HDK in the future.

Software Development Kits for the ICS-8551 are available for the VxWorks, Linux and Windows operating systems. Each SDK includes a kernel level driver, full API and application example code written in â&#x20AC;&#x153;C.â&#x20AC;? A Flash Loader utility is included to enable users to load FPGA cores to the onboard flash memory over PCI bus.

GE Fanuc Intelligent Platforms, Charlottesveille, VA. [www.gefanuc.com].

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January 2008

Dual Multiband Transceiver with FPGA Delivers Improved A/D Performance

A complete software radio system for connection to HF or IF ports of a communications system features significantly boosted analog performance. A major result is that the signalto-noise ratio and the spurious free dynamic range are improved by 10 dB in the Model 7141 from Pentek, when compared to many competitive products. The front end accepts two full scale analog HF or IF inputs on front panel MMCX connectors at +10 dBm into 50 ohms with transformer coupling into Linear Technologies LTC2255 14-bit 125 MHz A/D converters. A/D output samples are delivered into the Virtex-II Pro FPGA for signal processing or for routing to other module resources.

A TI/Graychip GC4016 quad digital down-converter accepts either four 14-bit inputs or three 16-bit digital inputs from the FPGA, which determines the source of GC4016 input data. These sources include the A/D converters, FPGA signal processing engines, SDRAM delay memory, and data sources on the PCI bus. Each GC4016 channel may be set for independent tuning frequency and bandwidth. For an A/D sample clock frequency of 100 MHz, the output bandwidth for each channel ranges from 5 kHz up to 2.5 MHz. By combining two or four channels, output bandwidth of up to 5 or 10 MHz can be achieved.

The Xilinx XC2VP50 Virtex-II Pro FPGA serves as a control and status engine with data and programming interfaces to each of the onboard resources including the A/D converters, GC4016 digital downconverter, digital up-converter and D/A converters. Factory-installed FPGA functions include data multiplexing, channel selection, data packing, gating, triggering and SDRAM memory control. The FPGA includes two PowerPC cores that can be used as local microcontrollers to create complete application engines.

The commercial version of the Model 7141 Multiband Transceiver with FPGA - PMC/XMC is priced at $10,995 and is also available in PCI and in 3U and 6U cPCI form-factors.

Pentek, Upper Saddle River, NJ. (201) 818-5900. [www.pentek.com].

industry wat c h

Data-Oriented Architecture

Data-Oriented Architecture: Loosely Coupling Systems into “Systems of Systems” Real-time systems today interact with other systems, both hard and soft real time as well as enterprise. Easily integrating them requires a fresh look at data-oriented interfaces.

by Rajive Joshi, Ph.D Real-Time Innovations Inc.

E

mbedded systems are no longer self-contained boxes of electronics and firmware. Many of them now have to interact with the rest of the world. They have to cooperate with each other, and in turn provide information to upstream systems so that other embedded systems, human operators and even the general public can see what is going on.

You can see this effect in a new generation of traffic-control systems. Data from traffic sensors does not just control how traffic lights and active road signs operate in real time. The same information is used to provide an overview of what is happening across a city to operators in a control center and fed to public information kiosks around the city to let people know what their journey will be like. It may even be streamed to drivers in their cars. This is the structure of a new class of “system of systems” and it requires a fresh design perspective to address the realities of integrating components from multiple independent providers.

Service-Oriented Architecture (SOA) has emerged as an effective paradigm in the enterprise computing space for addressing integration of software components. How do we utilize the SOA guiding principles of reuse, granularity, modularity, composability, componentization, interoperability and standards compliance to the design of embedded and real-time systems to achieve similar business benefits? What are the fundamental underlying principles that we can utilize to integrate embedded systems with enterprise systems, while optimizing end-to-end real-time performance? Can this be done without magnifying the ongoing operational and administrative costs?

We address these concerns by introducing the framework of “Data-Oriented Architecture,” which can be viewed as a SOA for real-time development and end-to-end integration of disparate independently developed software components. The data-oriented architecture framework results in “loosely coupled” software components with data-oriented interfaces that can be seamlessly

40

January 2008

Air Traffic Example Edge

Real-Time

Avionics

Airplane LAN

Real-Time Gateway Airport

Real-Time

Alarms

Control Tower LAN

Enterprise Gateway Enterprise

Figure 1

Enterprise Backbone

Airport LAN Arrival Time

The next generation of distributed systems is dynamic in nature and must meet the demands of constant availability, instant responsiveness, reliability, safety and integrity. They require integration of many platforms, systems and their data.

integrated using a high-performance standards-based communication middleware infrastructure, such as the Data Distribution Service (DDS).

A Real-Time System-of-Systems Scenario

The air traffic control example of Figure 1 involves a variety of disparate systems that must seamlessly operate as a whole.

On the “edge” is a real-time avionics system inside the aircraft, which may communicate with a control tower. The data flowing in this system is typically at high rates and is time-critical. Violating timing constraints could result in the failure of the aircraft or jeopardize life or safety.

The control tower is yet another independent real-time sys-

INDUSTRY Watch tem, monitoring various aircraft in the region, coordinating their traffic flow and generating alarms to highlight unusual conditions. The data flowing in this system is time-sensitive for proper local and wide-area system operation, although it may be a bit more tolerant of occasional delays.

In our simplified example, the control tower communicates with the airport enterprise information system. The enterprise information system keeps track of historical information, flight status and so on and may communicate with multiple control towers and other enterprise information systems. The enterprise system is not in the time-critical path and therefore can be much more tolerant of delays on arrival of data. This enterprise system is responsible for synthesizing a composite “dashboard” view, such as passenger information, flight arrival and departure status.

Key Integration Challenges

Such a system of systems must effectively deal with various issues. The information crosses trust boundaries, where each system is controlled and managed independently, and involves social, political and business considerations. The quantitative and qualitative differences in the data exchange, performance and real-time requirements across the disparate systems must be dealt with. For example, an edge system often carries time-critical data at high rates, some of which must eventually trickle into an enterprise system. Also, the architecture involves different technology stacks, design models and component life cycles. Many of these systems have different components evolving at different rates and being upgraded independently.

By their very nature, the systems under consideration are loosely coupled—minimal assumptions can be made about the interface between two interacting systems. The integration should be robust to independent changes on either side of an interface. Ideally, changes in one side should not force changes on the other side. This implies that the interface should contain only the invariants that describe the interaction between the two systems. As behavior is implemented by each independent system, the interface between them must not include any system-specific state or behavior. Therefore, the essential invariant is the information exchange between the two systems (Figure 2).

An information exchange can be described in terms of the information exchange “data model,” which involves the roles of data “producer” and “consumer” participating in the information exchange. Thus, when dealing with loosely coupled systems, a system’s interface can be described in terms of the data model and the role (producer or consumer) the system plays in the information exchange.

The systems on either side of an interface may differ in the qualitative aspects of their behavior, including differences in data volumes, rates, real-time constraints and so on. We use the term “impedance mismatch” as shorthand for all the non-functional differences in the information exchange between two systems.

Dealing with the impedance mismatch will involve considerations such as the quality of service that each side of the exchange expects and the architecture the overall system of systems adopts.

The independently managed systems can appear and disappear asynchronously, as they are started, shutdown, rebooted,

upgraded, or reconfigured. The environment can change dynamically, causing systems to react differently. In general, it is not possible nor is it practical to have a centralized administrator or coordinator of the various systems, especially at the granularity of asynchronous changes that may occur dynamically. Thus, each system must detect and react to dynamic changes as they occur.

Ideally, the information exchange infrastructure would be selfaware in the sense of being able to detect and inform the systems when changes occur in their connectivity with other systems.

System design in general may be viewed as a collection of interconnected components. Depending on the context and granularity of scale, a component may be, for example, a system of systems, an entire system within a system of systems, or simply an application in a system.

How do we create an unbreakable system software architecture that can accommodate disparate components maintained by Role “Producer”

Role “Consumer”

Independent System

Independent System Interface “Data Model” No system specific state or behavior

Figure 2

The interface between “loosely coupled” independent systems should not include any systemspecific behavior or state. It can include the “data model” of the information exchanged between the systems, and the role played by a system.

independent parties?

Data-Oriented Programming

An appropriate design model for building loosely coupled systems can be found in the principles of “data-oriented programming” or DOP as described by Eugene Kuznetsov of Datapower Technology (now part of IBM). It is based on the observation that the data model is the only invariant (if any) in a loosely coupled system, and should be exposed as a first-class citizen. In other words, data is primary and the operations on the data are secondary.

Data-oriented programming is complementary to objectoriented programming and provides a solid foundation for constructing loosely coupled systems. It can be seen as the theoretical basis for much of the recent work on service-oriented architecture (SOA) and Web services.

For a very simple example of what data-oriented programming entails, let us consider the task of registering a sale in a point-of-sale system. The participants involved in this task are: a customer, a store and the item sold. From a data-oriented viewpoint, we would define customer, store and item as publicly exposed data, and formally describe their structure as public metadata. We might define a message called regisJanuary 2008

41

INDUSTRY Watch ter _ sale that operates on the customer, store and item data to accomplish the task.

The consumer (or provider) of this message would have all the information necessary to execute the producerâ&#x20AC;&#x2122;s (or requestorâ&#x20AC;&#x2122;s) request, and its implementation is no longer tied to the behavior of the customer, store and item objects. If the definition of customer, store or item changes, the associated metadata is updated to inform the consumer of those changes, so that the data processing in the application logic can be adjusted accordingly.

Thus, this approach is robust to the changes in the data structure, as well as the behavior of the participants.

It is important to note that a design model by itself does not result in well-designed systems. Like object-oriented programming, data-oriented programming can also be misused and abused. Data-oriented programming provides the principles and guidance for building loosely coupled systems. However, design is fundamentally a human activity; models and tools can only facilitate the process.

Data-Oriented Integration Architecture

Large scale distributed systems of systems are often a mishmash of different architectural styles. They are systems created by independent parties, often using different middleware technologies, with misaligned interfaces. A naĂŻve approach to integrating such systems results in N*N point-to-point custom integrations for each pair of systems. This approach does not scale.

Yet, it is often the outcome in practice.

A better approach is to use a data-oriented programming approach and explicitly formalize the data and meta-data produced and consumed by a component or a system, then use a â&#x20AC;&#x153;data busâ&#x20AC;? to connect them. This results in a generic Data-Oriented Architecture framework (Figure 3).

Component

Component

Component

Topic Topic

Data Bus (DDS Middleware Infrastructure)

Component

Figure 3

42

Component

Component

A data-oriented integration architecture for developing loosely coupled applications.

Components can be added and removed independently, without any knowledge of other components. Data readers and data writers of data topics (data flows) can be created, used and deleted independently by a component, without requiring any centralized configuration or changes.

Direct data paths are automatically established between data readers and data writers of a topic, and managed by the middleware infrastructure.

January 2008

Event Processing Engine

Database

Web Service

Topic Topic

Data Bus (DDS Middleware Infrastructure)

Enterprise Service Bus (ESB)

Figure 4

Workflow Engine (BPEL)

Legacy Bridge

Commercially available â&#x20AC;&#x153;out-of-the-boxâ&#x20AC;? integrations of popular application platform components speed up the integration task by providing automatic mapping of the application platformâ&#x20AC;&#x2122;s native data representation to an underlying agreed upon semantic data model, in accordance with the principles of data-oriented architecture.

Such a data bus can accommodate a wide variety of architectural styles, and reduces the integration problem from an O(N*N) problem to an O(N). The popular architectural styles can be seen as specializations of the generic data-oriented architecture, by appropriate assignment of roles to the various components.

An example of middleware infrastructure able to provide a constantly available real-time distributed data bus is the RTI Data Distribution Service, which complies with the Object Management Groupâ&#x20AC;&#x2122;s DDS open standard specification. The DDS middleware infrastructure takes on important responsibilities and provides the underlying infrastructure to realize a loosely coupled real-time service-oriented architecture (SOA).

The data-oriented programming and design philosophy maps naturally to the data modeling and introspection capabilities provided by the DDS middleware. The resulting data-oriented architecture framework provides key capabilities that ease and facilitate the construction of system of systems and distributed systems in general. It addresses the challenges of (a) dynamic real-time adaptation and (b) scalability and performance. It can also facilitate integration by directly supporting the data-oriented design approach for loosely coupled systems, and thus aid in addressing (c) incremental and independent development and (d) impedance mismatch issues across systems of systems.

Leading DDS implementations provide a low-latency, highthroughput messaging and data caching infrastructure, utilizing direct peer-to-peer communications to optimize the â&#x20AC;&#x153;end-to-endâ&#x20AC;? performance. They do not require running any servers or daemons, thus there are no single points of failure or loading in a system either.

Rapid Development Using Integrated Application Platforms

Many application components can be rapidly developed by using off-the-shelf application platforms that have been a priori

INDUSTRY Watch integrated with the communications data bus infrastructure. Applications are organized around an agreed-upon underlying semantic data model, which is automatically mapped to the natural representation used by the application platform, in accordance with the principles of data-oriented design (Figure 4).

Useful application platform components include event processing engines to interpret and transform streaming real-time data in meaningful ways; databases for storing, retrieving and manipulating historical and reference data; enterprise service buses for integration with existing infrastructure; application servers for providing and using Web services; workflow engines for orchestrating processes; and reusable business-critical legacy components.

Leading real-time middleware vendors have already begun providing a complete end-to-end and real-time application development platform, comprising of components that integrate the real-time communications infrastructure with popular application platform technologies such as (1) event processing engines, to make meaning out of continuously flowing real-time data and (2) databases, to automatically map tables stored in â&#x20AC;&#x153;in-memoryâ&#x20AC;? or â&#x20AC;&#x153;on-diskâ&#x20AC;? into real-time data sources and/or sinks. The availability of such integrated application components can dramatically lower the risk in the integration phase and speed up the system of systems development effort by another order of magnitude.

The next generation of distributed systems will be loosely coupled systems that support incremental and independent development and are tolerant of interface changes; can systematically deal with impedance mismatches; work well in dynamically

changing real-time situations; and can scale in complexity while delivering the required real-time performance.

Popular architectural styles, including data flow architecture, event-driven architecture, data caching architecture and client-server architecture can be regarded as special cases of a generic â&#x20AC;&#x153;data-orientedâ&#x20AC;? architecture, by the appropriate assignment of roles and choice of quality of service in the interfaces between components. Data-oriented application architecture coupled with an appropriate standards-based communications middleware such as DDS can cut down the complexity of the integration problem, while preserving loose coupling and ensuring scalability.

An end-to-end and real-time application development platform that integrates useful application development technologies with a standards-based communications infrastructure such as DDS can further boost productivity and lower the cost of integration by reducing the overall risk and complexity of working with disparate systems.

Real-Time Innovations Santa Clara, CA. (408) 200-4700. [www.rti.com].

-

20° to +80°C

RUGGEDIZED USB VIDEO CAPTURE -ODEL COMPRESSES ANALOG VIDEO TO -0%' 7EIGHING IN AT ONLY OUNCES IT REDEFINES PORTABILITY ! RUGGEDIZED ENCLOSURE ENSURES USABILITY IN EXTREME ENVIRONMENTS

-0%' *0%' CAPTURE TO 53" FROM AN ANALOG VIDEO SOURCE AT $ RESOLUTION FPS .43# FPS 0!, 3YNCHRONOUS AUDIO CAPTURE 0ROGRAMMABLE MOTION DETECTION TEXT OVERLAY /3$ 0OWERED THROUGH 53" PORT #OMES WITH AN 3$+ THAT SUPPORTS MULTIPLE UNITS

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12/5/07 5:18:14 PM

January 2008

43

&TECHNOLOGY

Products

Core2 Duo EBX Single Board Computer with Multiple I/O Options

Targeted at system integrators who want a modular solution with high-quality 2D/3D graphics performance and high data throughput, a new EBX single board computer represents a step up in performance within the EBX series.

The PCM-9590 from Advantech offers the Intel Core2 Duo processor and is packed with two SATA II bus connectors, multiple I/O features, as well as flexible AT/ATX power input. The PCM-9590 is suitable for a wide range of embedded applications including digital surveillance, automation, security and gaming.

PCM-9590 combines numerous I/O features that include two SATA II interface, Dual Gigabit Ethernet, Dual Display (combinations: CRT + 36-bit LVDS, TV-Out + 36-bit LVDS, TV-Out + CRT), 7.1 Channel HD Audio, 6 x USB 2.0 and 4 x COMs. For expansion, there is one PCI-Express x16, one PCI-104 connector and one Mini-PCI slot allowing optional modules to be added on. The two onboard SATA II bus connectors offer a significant performance improvement of up to 3 Gbits/s over the older (soon to be phased out) IDE interface.

The PCM-9590 SBC with Intel Core2 Duo and 945GM chipset can support up to 4 Gbytes of DDR2 SODIMM memory. With Intel Graphic Media Accelerator (GMA) 950 chipset, the board also offers exceptional 3D graphic rendering and enhanced visual quality—perfect for the gaming market. PCM-9590 is also available with Intel Core Duo ULV U2500 1.2 GHz CPU, offering customers an alternative choice for fanless solutions.

The PCM-9590 was specially developed for Windows XP Embedded (XPe) operating system. To help customers integrate their own applications, Advantech’s SUSI API library provides access to functions such as Watchdog, GPIO, SMBus and many other functions. SUSI consists of a set of unified drivers and API that can help speed up the hardware/software integration process.

Advantech, Irvine, CA. (949) 789-7178. [www.advantech.com].

Small Core Duo Box Has PC/104 I/O Expansion

The concept of the “stand-alone rugged” box is coming ever more into demand in industrial solutions. Acces I/O Products has introduced its new Nano I/O Server CD (Core Duo). This fanless system is one of the smallest embedded systems available featuring an Intel Core Duo 1.66 GHz CPU. The system was designed to support an extensive collection of available PC/104 modules and external USB I/O devices. This allows for added versatility and is useful in a wide variety of applications.

The system is housed in a rugged, black anodized aluminum enclosure measuring only 5 inches wide, 6.25 inches deep and 3 inches high. The enclosure offers physical protection for industrial environments and features a bulkhead mounting provision. The unit is quietly powered by an included 12 VDC to ATX power supply with no fans. External connections provided include VGA, four USB 2.0 root ports, one RS-232 and one RS-232/422/485-selectable COM ports, PS/2 keyboard and mouse, 10/100 Ethernet and standard PC sound. This tiny system is the first fanless Intel Core Duo to highlight full PC/104, PCI-104 and PC/104-Plus I/O expansion. Systems start under $1,500. System pricing is dependent on choice of memory, disk media and I/O boards selected. OEM and volume pricing is available.

ACCES I/O Products, San Diego, CA. (858) 550-9559. [www.accesio.com].

44

January 2008

Low-Cost, Low-Power Compact Multi-Application Computer

A low-cost, compact PC-based controller is targeted for low-power embedded applications. The GEME-42000 from Adlink Technology is equipped with an Intel Ultra Low Voltage Celeron M processor (1.0 GHz) and up to 1 Gbyte DDR333 RAM, and can be controlled from remote locations and run continuously in critical applications including machine tools and digital video capture.

The GEME-42000 meets the needs of embedded controllers; it is compact, has front side access, is highly reliable and offers an

expandable architecture with optional motion, I/O and communication modules in PMC or PC/104 form-factors. Power supply options include standard AC power for stationary applications and DC power for mobile applications such as in vehicles. Supported operating systems include Windows XP Embedded, WinCE .Net and Linux. The GEME-42000 is priced at $925 with discounts in volume.

Adlink Technology Irvine, CA. (866) 423-5465. [www.adlinktech.com].

Power Supply Suits Noise-Sensitive, Rugged Apps

Combining a rugged power supply with low noise requirements is a challenge coming up more frequently as systems move to harsher environments. Meeting such needs, Bravo Electro Components has introduced its XUP Series of Modular / Configurable Power Supplies. The low noise/ripple of less than 10 mV (typical) and wide operating temperature of -40° to +75°C make these ideal for sensitive equipment in harsh environments.

The XUP family of products consists of four power chassis that are 2.5 inches tall and 7.3 inches deep. Output modules offer single and dual outputs with wide adjustment ranges to cover any voltage requirement from 1.5 to 350 VDC and around 200 Watts / 40 Amps per module. Outputs are adjustable from 5-100% using an external 0-10V trim voltage. VME/VXI signal sets, Single Wire Parallel, Remote on/off, Power Good and AC Fail Signals are available per output module or globally. Total Output Power is rated up to 700W at 90 to 180 VAC and 1,200 W at 180 to 264 VAC or total combined output power of the populated output modules.

Pricing starts at $487 for OEM quantities of 1200W four-Bay units.

Bravo Electro Components, Santa Clara, CA. (408) 733-9090. [www.bravoelectro.com].

Compact Embedded Computer with Stackable, Rugged PC/104 Modules

To meet the demand for a highly modular, compact and rugged solution suitable for the most remote, hostile and/or extreme environments—places where embedded platforms must operate seamlessly, Advantech has just added a new compact embedded computer to its ARK-4000 product series.

The ARK-4180 is a PCI-104-based solution with high vibration/ shock resistance and wide temperature capability. The ARK-4180 with Intel Celeron M 1.0 GHz processor can operate in temperatures ranging from -40° ~ 75°C, providing high processing performance in a compact, rugged enclosure.

The ARK-4180 is developed from PCI-104 stackable modules that are designed and qualified for demanding applications. The PCI-104 form-factor allows modules to stack vertically to provide a naturally rugged architecture. Each system is housed in a specially cast and milled solid aluminum block with thermal fins that help dissipate heat. Another feature is the specially designed fanless thermal solution with embedded heat pipes, which allow wide temperature operation between -40° ~ 75°C without active cooling.

Special brackets on the aluminum enclosure allow additional enclosures to be stacked to add I/O and other functionality, making the ARK-4180 the most flexible rugged solution on the market.

The ARK-4180 supports 6 x USB 2.0 and 2 x RS-232 connectors, 10/100Base-T Ethernet LAN and VGA for versatile connectivity. It supports one PCI-104 connector for expansion, and by adding another enclosure layer, up to two more PCI-104 modules can be stacked. The ARK-4180 is targeted to transportation and military applications, which depend on reliable data acquisition, along with resistance to extreme temperature fluctuations, shock and vibration.

PrPMC Board Marries 1553 and PowerPC CPU

The venerable MIL-STD1553 remains a popular interconnect technology for avionics as well as defense systems. The PMC is probably the most common platform for 1553. But Ballard Technology puts a twist on that with its latest MIL-STD-1553 offering that lets users decide on one or two dual redundant 1553 interfaces and then use the PowerPC function to handle responses, interact with other cards or just have the PrPMC as back-up. The new Ballard OmniBus PMC card offers a rugged, conduction-cooled solution for MIL-STD-1553 applications.

Ballard’s PMC card is available in commercial or conduction-cooled versions and offers users a monarch/non-monarch PrPMC with DMA and 1 or 2 dual redundant 1553 interfaces at an affordable cost.

The OmniBus 1553 PMC can be used as a peripheral to a host processor system, or it can operate as a stand-alone device utilizing the PowerPC embedded processor. The MIL-STD-1553 channels are implemented as hardware modules external to the processor. This results in the user having full utilization of the processor while protocol operations are autonomously performed in hardware. The OmniBus architecture ensures all schedules will be maintained and all data will be received on fully loaded 1553 databuses.

Ballard Technology, Everett, WA. (425) 339-0281. [www.ballardtech.com].

Advantech, Irvine, CA. (949) 789-7178. [www.advantech.com].

January 2008

45

Products&TECHNOLOGY Rugged Quad Channel Serial FPDP Board Rolls

The Serial Front Panel Data Port (sFPDP) interconnect has become the industry standard for high-speed serial communication in today’s advanced sensor-to-DSP systems. For its latest sFPDP offering, CurtissWright Controls Embedded Computing has introduced a new rugged, high-performance, quad channel Serial FPDP card that delivers sustained data rates up to 247 Mbytes/s on each of its four channels. The new FibreXtreme SL100/SL240 Serial FPDP card, based on Altera’s Stratix II GX FPGAs, connects distributed devices through a highly specialized communications protocol (VITA 17.1-2003) optimized for maximum data throughput.

The cards, available in both PCI and XMC mezzanine formats, are designed for use in applications that require high data rates such as digital signal processing, radar and sonar, medical imaging, range and telemetry systems. The sFPDP card off-loads the host processor, enabling data transfers to occur without the CPU overhead and non-deterministic latencies associated with many layers of complex software protocols. Availability of the FibreXtreme SL100/SL240 card is off-the-shelf in first quarter 2008.

LCD Controllers Are Ready for Rugged Duties

The drive toward net-centric operations in manufacturing and automation is driving up demands for compact and rugged display terminals. Digital View has introduced the HE Series of LCD controllers designed to comply with the strict standards required for the harsh environments encountered in rugged industrial applications. Both controllers feature wide tolerance power supplies, locking connectors and low-mass tantalum capacitors for maximum tolerance to shock and vibration, Mil-spec silicon resin conformal coatings, laboratory-certified operating temperature ranges of -40° to +80°C, and calculated MTBF in excess of 150K hours (HE-1600) and 200K hours (HE-1400).

Curtiss-Wright Controls Embedded Computing, Leesburg, VA. (703) 779-7800. [www.cwcembedded.com].

VXS Serial RapidIO Managed Switch for Multiprocessing Applications

A new VXS (VITA 41.2)-compliant Serial RapidIO managed switch card is designed to provide optimal support for VXS multiboard applications. The CRX800 from GE Fanuc Intelligent Platforms offers eighteen x4 Serial RapidIO (sRIO) payload ports, four x4 sRIO inter-switch ports and a PowerPC MPC8548 management processor that supports 128 Mbytes of flash memory and 256 Mbytes of SDRAM for very fast data throughput at up to 3.125 GHz per lane.

The CRX800, which is designed for a wide range of deployed signal- and data processing applications for land-mobile, airborne fixed and rotary wing, and naval surface and underwater platforms, is available in six ruggedization levels including air-, spray- and conduction-cooled for extended temperature operation as well as resistance to shock and vibration. For customers wanting to leverage the performance potential of serial switched fabrics in multiprocessing applications, but who are unable or unwilling to make the transition to VPX, the VXS-based CRX800 managed Serial RapidIO switch offers attractive price/performance, especially in combination with the DSP220.

The Tundra Tsi-578Serial RapidIO implementation supports operation speeds of 1.25 GHz, 2.5 GHz and 3.125 GHz per lane, while the onboard management CPU supports not only sRIO configuration but also BIT (built-in test) and switch management application software.

GE Fanuc Intelligent Platforms, Charlottesville, VA. [www.gefanuc.com].

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January 2008

The HE-1400 Series is a small footprint (4.2 x 3.6 inches), highly integrated controller with DVI and ARGB inputs. It supports both LVDS and TTL panels and is capable of supporting 4:3 format panels at up to SXGA resolution and 6:9 panels at up to WXGA resolution. The HE-1600 Series is a fully buffered, multi-sync interface controller providing direct analog and digital connection to a wide range of TFT panels up to UXGA resolution.

Pricing for Digital View’s new HE Series controllers is $110 for the HE-1400 and $180 for the HE-1600 in 1,000-piece quantities.

Digital View, Morgan Hill, CA. (408) 782-7773. [www.digitalview.com].

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Boundary Scan Platform Offers IEEE 1149.x Controller for LXI

A new series of specific JTAG/Boundary Scan controllers with LXI Interface (LAN eXtensions for Instrumentation) supports JTAG/boundary scan solutions compliant with IEEE Std.1149.x. The new series of Scanflex Boundary Scan Controllers (SFX-Controller) from Goepel Electronic is named SFX/LXI1149-(x) and includes three models for different performance classes. Joining SFX Controllers for PCI, PCIe, PXI, PXIe, USB/LAN and Fire Wire, the new SFX/LXI1149-(x) controller series is the seventh family of Scanflex controllers—available in three performance classes: A, B and C. The models differ in the maximum TCK frequency (20, 50 and 80 MHz, respectively) and in the degree of implementation of the enhanced Space chip set for high-performance scan operations. In contrast to conventional solutions, the integrated Fastscale technology allows an upgrade of the controller’s performance class “on the fly,” without intricate mounting of additional hardware. Standard features on all Scanflex controllers include Adycs II for signal path delay compensation, and Hyscan for dynamic splitting of serial TAP vectors and parallel I/O vectors.

SFX/LXI1149-(x) is a LXI Class-C device and provides a Triple Speed Ethernet-Interface (10/100/1000 Mbit/s). It is compliant with LXI hardware specification 1.1 and can be remote configured via the integrated Web browser.

In combination with the modular range of additional Scanflex components, LXI-based high-performance boundary scan systems with up to eight independent TAP can be configured and synchronized with other functional modules. All TAPs provide programmable input and output voltage as well as programmable input and output impedance. Furthermore, resources such as 32 dynamic I/O, two analog I/O channels, three static I/O and trigger lines are standard features.

The SFX/LXI1149-(x) controller series is fully supported in the industry-leading boundary scan software system Cascon from version 4.4.1 on, and can be integrated into all important software environments by means of pre-converted plug-ins. LXI has been a standard for the open integration of test and measurement devices since September 2005. Continuous development of this standardization is promoted within the frame of the LXI Consortium. At this time, more than 45 companies are members in this board.

Goepel Electronic, Jena, Germany. +49-3641-6896-739. [www.goepel.com].

XMC Board Sports Four Virtex5 FPGAs

FPGAs play a crucial role in applications such as WiMax front ends, radar and high-speed data recording and playback. Along those lines, Innovative Integration’s new X5-210M product is an XMC I/O module featuring four 14-bit 210 MS/s A/Ds with a Virtex5 FPGA computing core, DRAM and SRAM memory, and eight lane PCI Express host interface. Xilinx Virtex5 LX110T (SX95T when available) with 512 Mbyte DDR2 DRAM and 4 Mbyte QDR-II memory provide a very high-performance DSP core for demanding applications such as emerging wireless standards. The close integration of the analog I/O, memory and host interface with the FPGA enables real-time signal processing at extremely high rates exceeding 300 GMACs per second.

The X5 XMC modules couple Innovative’s Velocia architecture with a high-performance, eight-lane PCI Express interface that provides over 1 Gbyte/s sustained transfer rates to the host. Module functionality can be fully customized using VHDL and Matlab using the FrameWork Logic toolset, which includes full source code for user FPGA logic device, manuals, documentation and instructions for simulation under ModelSim and recompilation under Xilinx ISE. The X5-210M quantity one pricing is $9,995.

Innovative Integration, Simi Valley, CA. (805) 578-4261. [www.innovative-dsp.com].

6U VXS Multiprocessor Designed for Demanding DSP Applications

Featuring four single or dual core Freescale PowerPC 8641 system-on-chip nodes and a VITA 42.2-compliant XMC slot, a new 6U VXS (VITA 41.2) multicomputer is designed for demanding signal and data processing applications. The DSP220 from GE Fanuc Intelligent Platforms is available in six ruggedization levels including air-, spray- and conductioncooled for extended temperature operation as well as resistance to shock and vibration. It has already been selected for several major international military programs.

Designed for a broad range of applications such as land-mobile, airborne fixed and rotary wing, and naval surface and underwater platforms that require high-performance COTS multiprocessors, and providing the optimum platform for GE Fanuc Intelligent Platforms’ AXIS (Advanced Multiprocessor Integrated Software) environment, DSP220-based solutions can be scaled up to eighty 8641 nodes per chassis for the most demanding environments.

The DSP220 derives its performance from a number of key features.

Each PowerPC e600 core is clocked at 1 GHz, and each 8641 node supports two banks of DDR2 SDRAM with 256 Mbytes per bank, 2 Gbytes total per card, as standard. Up to 8 Gbytes SDRAM per board is optionally available.

PowerPC AltiVec support for advanced vector and floating-point operations is provided by each processor core. The multi-fabric data plane interfaces include Tundra Serial RapidIO to all 8641 nodes, XMC site and the system backplane along with two Gigabit Ethernet ports to all nodes and off board for optimum system throughput. System management and additional data movement options are supported over the VME64 2eSST interface. VxWorks and LynxOS board support packages are available.

GE Fanuc Intelligent Platforms, Charlottesville, VA. [www.gefanuc.com].

January 2008

49

Products&TECHNOLOGY IP Controller Incorporates Firewall Technology for M2M Applications

A cost-effective, firewall-on-a-chip solution allows machine-to-machine (M2M) devices to be safely connected directly to the public Internet. SecureGAP from Connect One safeguards proprietary information for application owners through security and data segregation, which serve as a gatekeeper and natural firewall between the host processor and the Internet as well as significantly cutting connectivity costs and simplifying deployment. This technology has been introduced in the CO2128, Connect One’s newest IP controller that provides Internet connectivity, encryption and security for a host processor or device. The CO2128 powers Connect One’s entire range of modules and device servers.

The CO2128 works as a coprocessor, offloading all security and communication aspects from the main processor. As a firewall between the host processor and the Internet, SecureGAP technology prevents intruders from tapping directly into the host processor’s data.

By maintaining a physical barrier between the public Internet and the application as well as encrypting data using SSL3, the CO2128 makes it safe to transfer data to and from any host processor over the Internet via 802.11b/g Wi-Fi, 10/100 BasedT LAN, GPRS, or dial-up connection. Architecturally designed into the CO2128 as an offload engine, SecureGAP serves as a trustworthy and reliable option for secure and efficient connectivity, and is technically superior to software firewalls installed on the host CPU. CO2128 supports LAN, Wi-Fi and all types of dial-up/wireless modems (AMPS, CDMA, CDMA2000, CDPD, GPRS, GSM, IDEN and TDMA cellular protocols). It includes a full secure TCP/IP stack, plus upper layer protocols like SMTP, POP3, MIME, HTTP, WAP, FTP, TELNET and SerialNet mode for serial-to-IP bridging. It also includes a Web server with two websites: one for the application and one for configuring iChipSec CO2128.

The CO2128 operates at an industrial temperature range of -40° to 85°C (-40° to 185°F) and is RoHS compliant.

Connect One, San Jose, CA. (408) 572-5675. [www.connectone.com].

Low-Cost Linux Controller Is Easy to Program

Because Linux is so familiar and accessible, it tends to be used during the development process, even when the final deployed system targets another OS. JK Microsystems has introduced their Omniflash controller, which provides the user with an array of I/O devices seamlessly supported by a pre-installed Linux 2.4 kernel.

The controller comes furnished with 10/100 Ethernet, two serial ports, battery backed clock/calendar, USB, digital I/ Os and stereo audio line level outputs. The 200 MHz ARM9 processor handles complex multitasking operations efficiently. Onboard memory includes 16 Mbytes of flash memory organized as an Ext2 file system and 32 Mbytes of SDRAM. The Linux operating system also includes over 150 standard Linux/Unix system utilities including ftp, tftp, telnet and vi. Also included in the development kit is a bootable Knoppix CDROM preconfigured with development tools to support the Omniflash. Quantity 100 price for the Omniflash controller is $129. Development kits are available for $199.

JK Microsystems, Davis, CA. (530) 297-6073. [www.jkmicro.com].

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Multi-Function cPCI Card Blends D/S Converters and Gbit Ethernet

A highly integrated, multi-function Compact PCI solution has a wide range of uses in high-speed and dataintensive applications.

North Atlantic Industries (NAI) has announced the availability of a 2nd generation, five-module, multi-function, singleslot cPCI card. This universal and highly flexible card eliminates the complexity and size constraints of using multiple, independent, single-function cards.

The 78CS2 cPCI card can accommodate up to five independent function modules.

It can be configured with NAI’s new highly efficient D/S converters—10 channels at 2.2 VA or 5 channels at 5.0 VA. The 78CS2 also incorporates a Gigabit Ethernet interface that can be used to transfer data to and from the board, without using the backplane bus.

This Ethernet port allows the board to be used as a stand-alone remote sensor interface, without the need for a separate computer board.

The 78CS2 is available with operating temperature ranges of -40° to +85°C and 0° to +70°C. Conduction-cooled versions with wedgelocks are also available. Pricing for 100 pieces of the 78CS2 starts at $3,500 each.

North Atlantic Industries, Bohemia, NY. (631) 567-1100. [www.naii.com].

Rugged Celeron M 1 GHz Single Board Computers

Two PC/104-Plus form-factor single board computers (SBCs) feature the low-power Intel Celeron M 1 GHz processor and Intel i855GME chipset in a rugged board design suited for mobile, high vibration, and extreme temperature embedded systems applications.

The CPU-1472 and CPU-1474 from Parvus deliver high computational performance and data communication capabilities for harsh environments (i.e., unmanned vehicles, aircraft, trains, buses) in a PC/104-Plus form-factor. The cards operate without any active cooling (fanless) over standard (0 to +60°C) and extended (-40° to +85°C) operating temperature ranges. Like other Parvus/Eurotech CPU modules, system DRAM is soldered on board to enhance shock/vibration resistance and each card is individually thermally qualified to ensure high reliability. A structural heat spreader plate

is integrated on top of each CPU module to dissipate heat from critical components.

The CPU-1474 features dual Local Area Network (LAN) controllers (Gigabit and Fast Ethernet) and four USB 2.0 ports, along with standard PC peripherals and I/O interfaces, including dual serial ports, TFT/LVDS interfaces, AC97 audio interface, keyboard and mouse ports, and IDE controller. The CPU-1472 is similar but provides a total of eight USB 2.0 ports and a single 10/100 Ethernet controller. These x86 CPU modules are compatible with Linux, Windows XP Embedded, and other popular operating systems.

Hardware development kits (DTKs) and accessories are available, as well as professional services for systems engineering of rugged box-level solutions tailored to customer requirements.

Parvus, Salt Lake City, UT. (801) 483-3426. [www.parvus.com].

4-Channel 50 MS/s 8bit Digitizer / Oscilloscope on PCI Express Card

Two new 8-bit digitizer / oscilloscope PCI Express cards support two and four 50 MS/s channels. Introduced

by Strategic Test, the UF2e-2020 has two 50 MS/s channels, while the UF2e-2021 has four 50 MS/s. Each channel has its own 8-bit ADC for simultaneous sampling, seven programmable input voltage ranges from ±50 mV to ± 5 V, offset adjustment to 400% and both 50 ohm and 1 Mohm input impedances. Unique features of the UF2e-2020 and UF2e-2021 include the option for dual-timebase sampling, synchronous digital inputs, asynchronous digital I/O and the ability to synchronize up to 542 channels.

With up to 4 GigaSamples of onboard memory, the cards are able to record signals for 40 seconds on two channels and 20 seconds on four channels. Alternatively, captured data can be streamed continuously to PC RAM or hard disk(s) at up to 120 MSamples/s over the PCIe bus. Drivers and programming examples for Microsoft Windows Vista, XP64, XP and Linux (RedHat, Fedora, SuSe, Sarge) are supplied with the card, as well as the SBench 5.3 oscilloscope program. SDK’s for Matlab, LabVIEW, Agilent-VEE, DASYLab and LabWindows/CVI are available as options. Prices start at $3,190 with volume/OEM discounts available.

Strategic Test, Woburn, MA. (617) 621-0080. [www.strategic-test.com].

Trio of Storage Systems Target RAID and SBOD

Radar and reconnaissance applications all hunger for ever more robust digital signal analysis and data collection. VMetro has announced the availability of three storage devices for use with its Vortex data recording solutions.

The VS-SBOD 3U (shown) is a 16-disk (up to 6.4 Terabytes) storage system that offers a flexible solution with high performance through the use of a switched topology backplane and redundant quad 4 Gbit Fibre Channel initiators to the drives. The VS-FY5x 2U is a 12-disk (up to 9.0 Terabytes) RAID storage system that utilizes FC to SAS/SATA single or dual RAID Controllers to provide high performance and scalability at affordable pricing. The VS-FY5x supports various RAID levels and has an optional 2U expansion chassis that doubles the storage up to 18.0 Terabytes. The third offering is the VS-F48D 4U, a 48-disk RAID storage system that utilizes FC to SAS/SATA dual RAID Controllers to provide up to 36 Terabytes of storage capacity with low power consumption per Terabyte. It supports various RAID levels and has an optional 4U expansion chassis that doubles the storage up to 72 Terabytes.

VMetro, Houston, TX. (281) 584-0728. [www.vmetro.com].

January 2008

51

Products&TECHNOLOGY PC/104 SBC Meets Low-Power Needs

To meet the continuing need of many industrial automation (IA) systems for a low-cost, stable x86-based PC/104+ single board computer, Acrosser Technology has introduced its AR-B8020, a low power PC/104+ single board computer. Many of the original low-end x86 CPU processors are currently being phased out. Although these products had a long life cycle, these CPUs are now End of Life (EOL). Due to recent EOL announcements on CPUs, Acrosser has developed the AR-B8020 to meet the demands of those still in need of these low-power devices.

The RDC is a reliable, long-life CPU that not only meets customers’ performance requirements, but also their low-cost targets. For these reasons, Acrosser chose the RDC 8610 to be the core of the AR-B8020. AR-B8020 is a single-chip solution (CPU and Chipsets), providing quality performance in a low-cost format. Also the small PC/104+ form-factor facilitates integration into compact environments.

The CPU is the 32-bit 8610 from RDC running at 133 MHz and the AR-B8020 is designed on the PC/104+ form-factor (90 x 96 mm or 3.5” x 3.8”) with onboard PC/104 and PCI-104 connector for expansion boards. The board is software compatible with DOS, Linux and Windows CE. I/O support includes two USB 2.0 ports, one 10/100 Ethernet port, three COM ports (one RS-232, two RS-232/485), one FDD, 1 x 44pin IDE and one 8-bit GPIO. Acrosser Technology, Cypress, CA. (714) 903-1760. [www.acrosser.com]

microATX SBC Supports Active Management Technology

A new Intel Q965-based industrial microATX motherboard supports a selection of processors and implements Active Management Technology (AMT) to enable remote management. The AIMB-564 from Advantech is an LGA775 socket microATX motherboard powered by an Intel Q965/ ICH8DO chipset. It supports Intel Core2 Duo, Pentium D, Pentium 4 or Celeron processors for low-wattage, best-in-class computing performance. It can handle up to 8 Gbytes of dual-channel DDR2 533/667/800 MHz memory, with a 1066/800/533 MHz FSB. Multitasking capacity and memory management are built in, along with high-performance video and audio. With full support of Windows Vista 64-bit and DirectX 10, this board is ready for enhanced high-end media, with 3D visual detail and onboard 8-channel high-definition surround sound.

AIMB-564 implements Trusted Platform Module (TPM) support. Advantech provides an optional TPM chip that can be plugged into the board for the added security of boot drive encryption, key and password storage, digital authentication and hardened file protection. Another TPM benefit is high-quality random number generation, which can be very useful for gaming machines. Also implemented is Intel Active Management Technology that allows administrators to remotely diagnose, manage and cure systems, regardless of the system’s power state or OS condition.

AIMB-564 combines processing power with mass storage, I/O and memory options. Seven SATA II connectors, along with robust ICH8DO RAID 0, 1, 5 and 10 support, are appealing to surveillance applications, where large amounts of data need to be retained. If seven internal hard drives are not enough, an eSATA connector allows the attachment of an external JBOD stack. In addition to the onboard VGA, one PCIe x16, one PCIe x4 and two PCI slots provide for graphics, capture and add-on cards. Ten USB 2.0 ports, one serial port, one parallel port and two IEEE 1394 connectors endow this board with abundant connection opportunities. LAN connectivity is covered by one 10/100/1000 Base-T Intel 82566DM Gigabit Ethernet port. With five years minimum of assured product availability, it fully supports Microsoft Windows XP, 2000 and Vista and DirectX 10. Pricing starts at $248.

Advantech, Irvine CA. (949) 789-7178. [www.advantech.com]

52

January 2008

AMC Processor, 2.16 GHz Intel Core 2 Duo CPU, up to 8 Gbytes DRAM

A high-performance Advanced Mezzanine Card (AMC) single-width, fullheight processor module is suitable for AdvancedTCA, MicroTCA and proprietary platforms. The AM 110/10x from Concurrent Technology supports the 2.16 GHz Intel Core 2 Duo T7400 processor (soldered) or 1.5 GHz Intel Core 2 Duo L7400 processor (soldered), each with 4 Mbytes L2 cache shared between the cores, both processors can support 64-bit operating systems. Concurrent Technologies’ composite benchmark test on the AM 110/01x shows the relative CPU performance of the 2.16 GHz processor to be 1.8 times faster than the 1.5 GHz. To enhance overall memory and I/O performance the AM 110/10x utilizes the Intel 3100 chipset, which combines server-class memory and I/O controller functions into a single component. The Intel 3100 chipset interfaces to up to 8 Gbytes DDR2-400 ECC memory, via two registered SODIMMs, with a peak memory bandwidth of 3.2 Gbytes/s.

The AM 110/10x is designed in compliance to AMC.0 (including full hot swap and IPMI capabilities), AMC.1 Type 8 (PCI Express x8), AMC.2 Type E2 (2x Gigabit Ethernet) and AMC.3 Type S2 (4x Serial ATA150 ports). The module also features two USB 2.0 ports and an RS-232 port. There is a further Gigabit Ethernet port, USB 2.0 port and RS232 port accessible via the front panel. An optional onboard USB flash disk is available in a range of capacities up to 8 Gbytes. For ease of integration, many of today’s leading operating systems are supported including Linux, Windows 2000, Windows Server 2003, Windows XP, Windows XP Embedded and QNX. Concurrent Technologies, Woburn, MA. (781) 933-5900. [www.gocct.com].

2eSST, 6U VMEbus SBC Offers Flexibility, High Data Rates

A new 2eSST, 6U VMEbus single board computer (SBC) reaches a data transfer rate of up to 320 Mbytes/s using a Tundra TSI148 bridge controller. The A17 from MEN Micro is built around Freescale’s new PowerQUICC-III PowerPC MPC8548 consisting of a highly integrated e500 core with an FPU (floating point unit) and MMU (memory management unit) as well as L2 cache support. The A17 provides clock frequencies of up to 1.5 GHz, offering advanced technology exceptional performance levels while maintaining backward compatibility with older standards such as VME64X and VME. Using only one slot, the A17 can function as either a master or slave in legacy VME environments.

The soldered 2 Gbytes of fast ECC-controlled DDR2 SDRAM memory firmly withstands shock and vibration, making the A17 suitable for mobile applications. The flash disk for program storage is also soldered, and the non-volatile FRAM is suitable for applications that require low power consumption. The A17’s front panel has two Gigabit Ethernet and two COM interfaces accessible via an RJ45 connection. Two additional Gigabit Ethernet channels are available at the optional P0 rear connector.

The board offers two PMC slots at up to 64-bit/66 MHz. One of the mezzanine slots supports rear I/O and can be used for XMC modules with a PCI Express x1, x2, x4 or x8 link. The second PMConly slot, connected to the onboard FPGA, can also be used for individual additional functions implemented in the FPGA. The A17 operates over a temperature range of -40° to +85°C (-40° to +185°F), is RoHS compliant and comes with board support packages (BSPs) for Linux, VxWorks and QNX based on MEN’s own “BIOS” for PowerPC processors (MENMON). Pricing starts at $2,397.

MEN Micro, Ambler, PA. (215) 542-9575. [www.menmicro.com].

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HOW WELL DO YOU KNOW THE INDUSTRY?

WWW.EMBEDDEDCOMMUNITY.COM

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January 2008

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11/13/06 5:55:59 PM

LatticeECP2M FPGAs More of the Best

ϑ 4 to 16 SERDES (3.125Gbps) Only 100mW per channel

ϑ Up to 5.3Mb of Block and Distributed RAM

Supports PCI Express, Ethernet

ϑ Up to 95K LUTs

& other packet protocols

ϑ DSP Blocks

With multiply and accumulate

ϑ PLLs and DLLs

For optimized frequency synthesis & clock alignment

ϑ Flexible I/O Up to 601 I/O

ϑ Pre-Engineered Source Synchronous I/O Up to 840Mbps LVDS I/O

ϑ Superior Configuration Options

• Encrypted bitstream support • TransFR™ technology for easy field updates • Dual boot support

LatticeECP2M: The First Low-Cost FPGA with 3Gbps SERDES LatticeECP2M FPGAs give you “More of the Best” for less.

Visit our website at www.latticesemi.com. You’ll find information about Lattice’s complete line of FPGAs, including LatticeECP2M, LatticeECP2™, LatticeSCTM Extreme Performance System Chip FPGAs, LatticeXPTM non-volatile FPGAs and many more. If you haven’t looked at Lattice FPGAs lately, look again – things have changed.

Get more for less with Lattice’s new LatticeECP2M™ family. No other low-cost FPGA offers up to 16 SERDES channels with full-duplex serial data transfers at rates up to 3.125Gbps. Best of all, each SERDES channel operates on a cool 100mW at maximum speed.

The LatticeECP2M family offers even more, including up to 5.3Mb of RAM, high-speed DSP blocks, 533Mbps DDR2 memory interface and SPI4.2 support. Plus, 128-bit AES Encrypted Bitstream support and Transparent Field Reconfiguration (TransFRTM) allow you to keep your designs secure and easily upgradeable even after your product has shipped.

For design software and a FREE FPGA handbook go to latticesemi.com/ecp2m

©2008 Lattice Semiconductor Corporation. All rights reserved. Lattice Semiconductor Corporation, L (& design), Lattice (& design), LatticeECP2M, LatticeECP2, LatticeSC, LatticeXP, TransFR, and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries, in the United States and/or other countries. Other marks are used for identification purposes only, and may be trademarks of other parties.

Mass Storage Modules for VMEbus and CompactPCI®

Gigabit Ethernet I/O Chassis with 12 “Cube”-Compatible Slots

A new Ethernet I/O chassis from United Electronic Industries is based upon the electronics in the company’s popular “Cube” I/O chassis. Called the RACKtangle, or more officially, the DNR-12-1G, the new rectangular form-factor chassis increases the number of I/O slots from six to twelve, in a compact and rugged 3U chassis.

As the RACKtangle is electrically compatible with the “Cube” formfactors, all of the I/O boards available in that form-factor are also available for the RACKtangle. With over 30 I/O modules available, there will be a configuration suited for almost any application requirement.

The RACKtangle’s 12 I/O slots provide up to: 300 analog inputs, 384 analog outputs, 576 digital I/O, 96 counter or quadrature channels, 144 ARINC-429 channels and/or 48 Serial or CAN-bus ports.

Software for the RACKtangle is provided in the UEIDAQ Framework. The Framework provides a comprehensive, easy-to-use API that supports all popular programming and operating systems including Windows, Vista, Linux and most real-time operating systems (e.g., QNX, RTX, RT Linux). Finally, the board is fully supported by LabVIEW, Matlab/Simulink, DASYLab or any application supporting ActiveX, OPC or Modbus TCP control. Pricing for the DNR-12-1G is $4,250.

PMC CompactFlash Module Two Type I/ Type II CF Sockets

See the full line of Mass Storage Products at

www.RedRockTech.com

or call Toll-Free: 800-808-7837 Red Rock Technologies, Inc. 480-483-3777

United Electronic Industries, Walpole, MA. (508) 921-4600. [www.ueidaq.com].

XMC/PMC Digital Transmitter Module

edrock_04.indd 1

Targeted at the development of advanced, high-performance solutions for Software Defined Radio (SDR) applications, the ICS-8560 rugged XMC/PMC digital transmitter module from GE Fanuc is designed for use with the company’s V4DSP 6U VME FPGA/PowerPC digital signal processing platform. The ICS-8560 offers two-channel operation with sampling frequencies up to 400 MHz. Featuring the Xilinx Virtex-4 (FX60 or FX100) FPGA in combination with onboard DAC (Digital-Analog Conversion) resources, the ICS8560 allows VHF waveforms to be processed and converted directly on the XMC module.

Available in five ruggedization levels, the ICS-8560 includes two transformer-coupled analog outputs with 16-bit resolution (Analog Devices AD9726) and supports sampling frequencies up to 200 MHz in single data rate mode and up to 400 MHz in double data rate mode.

Algorithms such as modulation and digital up-conversion can be developed for implementation in the user-programmable Virtex-4, using the supplied Hardware Development Kit (HDK). The ICS-8560 provides the user with up to eight lanes of high-speed serial I/O via a single XMC connector, which is directly connected to the RocketIO buffers of the Virtex-4, providing transfer rates of up to 3.75 Gbytes/s with XMCequipped carrier cards. Windows, Linux and VxWorks software drivers are available.

GE Fanuc, Charlottesville, VA. [www.gefanuc.com].

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1/15/08 11:27:48 AM

NEWS, VIEWS &

Comment January 2008

Embedded Computer Business on Fast Track Despite Economic Forecasts Market Performance

Happy New Year. Now that we’ve rounded the beginning of the New Year, it’s time to begin to put the preceding 12 months in perspective. Overall, from the many vendors and OEMs that I’ve spoken to, it’s been a good year—with, of course, exceptions.

First off, many vendors and OEMs report continuing erosion in the average selling prices of systems and subsystems—particularly in the non-military sector. Smaller, more compact, rugged and less expensive (as reported in these pages recently) seems to be the trend. The good news? Volumes are up across almost all applications.

Second, there’s been a trend toward much shorter life cycles and a resultant change in product lead times. OEMs continue to look for faster time-to-market, putting pressure on suppliers for quick design turnarounds. Even in the military, vendors are seeing shorter projected life cycles and a requirement for faster turnarounds. However, the military has some special exceptions including federal budget considerations, war-time spending and changing priorities. (For a complete update on the military market, look in the January issue of our sister publication, COTS Journal.

Overall, the embedded-computer sector (modular computer subsystems and systems) grew at some 8% with all applications included for the past 12 months (December estimated). The military was a little slower, enjoying only a 7% increase, while all other applications combined increased almost 9%. Of the other application areas, the greatest growth was in automation and control, medical, and transportation, with the growth in communications bringing up the rear. And while the generic media keeps talking recession, there is little sign of it in the embedded-computer business, as most vendors and OEMs queried re-

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January 2008

5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0

Figure 1

2001

2002

2003

2004

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2006

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2008

The embedded-computer industry has been growing dramatically over the past several years, enjoying an average growth rate of close to 10 percent (9.566). The military side of the market accounted for a little over 8% while the balance, a little over 10% growth, is attributed to everything else including communications, medical electronics, automation and control, transportation, scientific exploration, simulation and retail.

sponded that they anticipate 2008 to equal or exceed 2007 with an estimated increase larger than that from 2006 to 2007. Much of that increase is calculated to be outside of the military, while the military will continue to see growth in the 8% area. Figure 1 shows the overall growth of military and non-military markets for the past seven years.

One of the measurements we try to keep abreast of is the book-to-bill ratio. It generally provides some indication of industry growth. While the shrinking turnaround times have resulted in a far flatter B-to-B than in the past, (parts ordered and shipped

in the same month have a ratio of 1:1) the volatility of the military market results in a more dramatic value. Figure 2 looks at the book-to-bill ratio for the entire embedded-computer market over the past year.

On the Semiconductor Front…

In what seems to me a strange move, AMD management “apologized to Wall Street” for, as one analyst put it, “botching its handling of its high-end chip line.” Among other things, it hit a snag with its four-core Barcelona chip—putting off general delivery from mid-2007 until sometime in 2008. Other high-end chips have failed to reach top speeds that improved chips from rival Intel are reaching. And, its acquisition of graphics chip maker ATI has resulted in a significant write-off for good will. (In other words, AMD simply paid too much.)

In other chip news, ON Semiconductor has agreed to purchase AMI Semiconductor (AMIS). ON, it’s to be remembered, is an early spin off of the analog and discrete device sector (audio and power management devices) of Motorola Semiconductor.

The balance of Motorola’s semi business was spun off as Freescale. AMIS is expected to contribute products and capabilities in the medical and military/aerospace markets to complement On’s existing automotive and industrial business.

And, China’s Semiconductor Manufacturing International Corp. plans to invest an initial $450 million in a new wafer fabrication plant in Shanghai. While we sometimes tend to think China is still producing chips on 3” and 4” wafers, with singledigit micron design rules, the new facility will use 12” wafers and is expected to use aggressive geometries. The company plans to increase the investment to $2 billion over the next few years.

In Flight Wi-Fi

Airlines continue to look to provide Wi-Fi on their aircraft.

Back in 2006, there was a big effort by Boeing that involved many embedded-computer makers supplying a company called Connexion. The service failed, according to analysts, because the satellite-based service was too expensive to install and operate.

Now several carriers are looking to air-to-ground connections to avoid expensive satellite fees. Jet Blue’s LiveTV subsidiary paid the FCC $7 million for wireless spectrum that communicates with about 100 cell towers across the country. It’s been running this service, with partners Yahoo and RIMM, in one aircraft since December 11.

Others have planned more broad-based approaches. Aircell licensed a larger frequency band for $31 million and plans to offer broader Internet services for about $10 a flight—what Boeing was going to charge for the first hour. Alaska Air is going with a satellite-based system for its Alaska-to-Hawaii flights using services from Row 44, which uses an existing satellite network. All good candidates for rugged, compact embedded computers.

1.3 1.2 1.1 1 0.9 0.8 0.7 Figure 2

The classic book-to-bill ratio is often a predictor of future growth. Because of the shortened lead times, particularly in the non-military sector, the book-to-bill ratio has flattened out compared with earlier years.

of a possible recession for the slowdown. Forrester expects U.S. tech spending growth of only 5.3% compared with 6.4% last year.

IDC cut its worldwide tech-spending forecast to under 6% from last year’s number of almost 7%.

Intel Softens Push on Living Room Brand

Back in 2006, Intel planned to take America’s living room by storm with its Viiv effort. Now, only two years later, Intel says it’s dropping the idea of promoting the Viiv on Internet video programming and living-room devices that connect to TVs. Instead the company plans to use a modified version of the brand on entertainment-oriented computers using its dual-processor chips.

Also look for Intel to come up with new devices to compete with cell phones offering a full Web experience. The new gadgets are expected to be a little larger than a cell phone yet still fit in a shirt pocket. Intel will also be pushing its flash memory despite an extension in the closing of a deal with STMicro for a new joint venture called Numonyx, combining the companies’ flash memory chip businesses.

Tech Spending Down for ’08

According to some, market turmoil and high energy costs could slow down tech spending for 2008. Research firms IDC and Forrester have revised down their tech-spending forecasts for next year. They blame subprime-mortgage fears, turmoil in the U.S. financial markets, rising energy costs and the prospect

Warren Andrews Associate Publisher January 2008

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January 2008

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