EEWeb Pulse - Volume 94 by EEWeb Magazines

Dan Kinzer CTO of Fairchild

DDR4 Design Considerations SL Series by Magna-Power Analysis of TDC Convertersâ&#x20AC;&#x201D;Pt. 2 Electrical Engineering Community EEweb.com

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TABLE OF CONTENTS

Dan Kinzer

CTO OF FAIRCHILD SEMICONDUCTOR A conversation about the company credited with starting the Information Age.

Featured Products

SL Series by Magna-Power: Pushing the Limits of Programmable Power

How Magna-Power’s unique approach to manufacturing yields a diverse line of programmable DC power supplies.

DDR4 Design Considerations BY MIKE MICHELETTI WITH TELEDYNE LECROY Why more double data rate (DDR) developers are targeting DDR4 technology for a variety of applications—from high density blade servers to high performance workstations.

Design & Analysis of TDC Converter Architectures - Part 2

BY UMANATH KAMATH WITH CYPRESS This installment goes through the transistor-level implementation of a TDC in an 80nm process.

RTZ - Return to Zero Comic

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INTERVIEW

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EEWeb PULSE How did you get into engineering? I always loved math and science, even as a young boy. I applied to several of the top science and engineering schools, because I wanted to be involved in something related to science. I chose engineering at Princeton over CalTech and MIT, and I joined the Department of Aerospace and Mechanical Sciences. In that department, I studied a large variety of engineering and science courses, and found them all very interesting. I took a program in engineering physics because I found physics especially fascinating. It is so fundamental to understanding the way the universe operates. That actually led me into solid-state technology and eventually into power semiconductors. In 1978, I joined International Rectifier, which was my first permanent position, and worked on the development of their first family of power MOSFETs. From there I moved into solid-state optocoupled relays and high-voltage and high-power ICs, where I was involved in process and

From there I came to Fairchild, where I was able to continue to work in the power area with a world-class company. I was also able to get involved with the mobile business and began working with the technology development team to improve the integrated circuit processes. Since I’ve been here at Fairchild, I’ve put a lot of focus on improving the power device technology across the range of power and high-density power packages and modules.

included the rapidly growing power MOSFET business, standard logic, standard linear, analog switches, and a variety of other analog and discrete product lines.

Could you give us a little history of Fairchild?

Fairchild has its headquarters in San Jose, a major IC fab and administrative office in Portland, Maine, with other fab locations in Pennsylvania, Utah, and South Korea. Our internal assembly sites are in China, Malaysia and the Philippines. In addition, we have several major wafer fab foundry and assembly subcontractor relationships. Our factory in Suzhou, China is a worldclass power packaging and power module manufacturing center. We continue to push the state of the art in power and mobile applications and technologies.

Fairchild’s history goes back to 1957. Many credit the origins of Silicon Valley to the founders of Fairchild. Many believe that Robert Noyce’s silicon integrated circuit launched the Information Age. From our origins until now, we continue to be thought of as leaders and innovators in the industry. From the original Fairchild, our leadership spun-off into other companies, including National

“Our IP is inside virtually every smart phone in the world, and we ship more than 3 billion units per year to handset and tablet OEMs.” technology development as well as product design. In addition to power devices, I was spending a lot of time creating package technologies and IC designs. I eventually became the Vice President of R&D at International Rectifier and held that position from 1989 until 2007.

Semiconductor, Intel, AMD, LSI Logic and many others. In the 1980’s, Fairchild was acquired by Schlumberger, and then National in the early 1990s. Then, in 1997, Fairchild was spun back out from National as a stand-alone brand and company. At that time, Fairchild’s offerings

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The re-formed company went on to acquire the power semiconductor businesses of Harris and Samsung, which added factory locations in Pennsylvania and Korea. This brought high voltage power discretes and high voltage analog ICs, as well as automotive products into the portfolio.

What are of some of Fairchild’s main products? In broad terms, our offerings fall into two main categories - power semiconductor solutions and mobile semiconductor solutions. In mobile, Fairchild is a mobile technology leader, offering an unmatched portfolio of analog and power technologies in both standard and customized semiconductor products for mobile applications. These include ICs that offer combinations of analog switches, load sensing, power management, audio, lighting, communication, and sensors, among other functions. Our IP is inside virtually every smart phone in the world, and we ship more than 3 billion units per year to handset and tablet OEMs. We are also adding

INTERVIEW MEMS inertial sensors to our portfolio of mobile offerings. In our power portfolio, we have devices that start at about 12-volts and go to about 1400-volts. This includes one of the main families, our PowerTrench(R) MOSFETs, which are lower voltage devices in the under 200-volt range. We have a MOSFET technology that few other companies have, called shielded-gate technology, which greatly improves the power density, switching performance, and efficiency of trench power MOSFETs. That’s definitely an area of a lot of interest. In higher voltage areas, we have a strong lineup of super junction MOSFETs in the 600-650V range. In addition, we have some leading technologies in AC to DC converters up to 1 kilowatt, and motor drives up to 5 kilowatts. For higher power levels, we have our IGBTs. We’ve got a variety of technologies there—our latest technology is called field stop technology. We have leading edge performance in 600- to 1200-volt IGBTs for motor drives, renewable energy, and industrial and automotive power train applications. We are a leading supplier of power modules that use direct bonded copper on ceramic and transfer molded packaging technology. This technology allows us to manufacture SPM® smart power modules that include drive, sense, and protection features as well as power—with highly robust cycling performance and excellent thermal characteristics. Recently, we announced our newest technology, silicon carbide. Silicon carbide technology will be part of the next generation of power systems, allowing more power in less space and the ability to deliver more performance per unit cost. For more than 50 years Fairchild Semiconductor has focused on

“Our largest core mission concerning energy efficiency is something that we get very excited about and we value the contribution that makes to society in general.”

customer success. Our commitment to their success drives us to design, manufacture, and supply power and mobile semiconductor technologies to make home appliances more energy efficient, enable mobile device manufacturers to deliver innovative new features, and boost the efficiency of industrial products. Our semiconductor solutions for automotive, mobile, LED lighting, and power management applications help our customers achieve success every day. What kinds of products are you targeting for your silicon carbide technology? The device that we led with is a 1200volt bipolar transistor. We selected the bipolar transistor to start with because it has the lowest conduction loss of any technology, so we can get the most current out of a given chip size. It switches extremely fast—as fast as any device currently can—so it can also operate at a relatively high frequency for highpower applications. Normally, these applications may run at 5 or 10 KHz, but with these silicon carbide bipolar transistors, we can actually take that up to 30, 40, 50, even 100 KHz in some applications. We will offer diodes that complement these transistors, and

we package them in plastic, high temperature discrete, and power module packages. Is there additional drive circuitry required to implement this new technology? Yes. Most designers are not used to driving bipolar transistors because they require an input current. One of the good things about this silicon carbide technology, compared to what people remember in silicon bipolar technology, is that the current gain is very high, so you don’t have to put that much current into the base to get what you want out—the gains are in the range of 100, typically. The power loss is not a very big factor— it’s about a tenth of a percent of the output power. People do need to remember how to drive the base of a power transistor because many are used to drive MOSFETs and IGBTs, which are voltage-controlled. Do you have app notes or other resources to help engineers who aren’t familiar with using these transistors? Specific to silicon carbide technology, we have resources from applications notes, reference designs, evaluation boards and starter kits, to field Visit www.eeweb.com

EEWeb PULSE application engineers who are available to work with our customers. In high-power applications, a lot of people use pretty powerful bipolar power supplies in driving IGBTs. Those same supplies can be used in driving the BJT with a specialized drive circuit. We are also working on a specially optimized integrated circuit for driving these devices as well. What are some of the other design tools and resources Fairchild offers? Fairchild’s design support extends to all our product lines, not just the new silicon carbide technology. First, our application engineers are available to customers, both in the factory and field. We have an online design center that is part of our Global Power ResourceSM - a worldwide network of power design centers, power seminars, and a suite of online design and educational tools to help designers solve their design challenges and speed timeto-market. We are well known for our travelling Fairchild Power Seminar series which brings design support right to the customer. Our application notes and product usage guides are available online. You can also easily get samples through our on-line sample program. We also have online design tools as well that you can use for some power supply applications. Could you tell us a little about your super junction devices? Fairchild’s super junction MOSFETs range from resistances of around 40 milliohms up to a couple of ohms and currents in the 5- to 75-amp range. We also have both 600- and 650-volt devices, as well as devices optimized for fast recovery of the internal diode, and fast recovery-type

devices in different speeds. We have versions that are optimized for the fastest possible switching, therefore highest efficiency, and others that are optimized to be a little easier to drive with a little bit slower transitions and less EMI. People can choose which kinds of devices they want out of those families. We’re also perhaps the only company that offers two main types—in both cases, you have super junctions that consist of p- and n-type columns arranged in alternating fashion to form the high voltage blocking layer. There are different ways to form that. One of those ways is a deep trench etching and refill and the other way is with multiple p-type buried layers stacked up on each other, which is a more conventional approach. What are some of the exciting developments you are working on in the upcoming year? Fairchild is always innovating and developing next generation solutions that will help our customers succeed. We see the three megatrends being energy, mobility, and the cloud. We want to be leaders in all these areas. In mobile, our products are in virtually every smart phone device. We’re in battery charging circuits, we’re in core power, we’re in powering RF amplifiers, we’re in USB ports, audio, and many more. We’re developing MEMS for inertial sensing as well. We’re very excited about all these contributions we’re making in handheld devices. In the past year or two, my focus has been on system-wide energy efficiency, from the smart-grid and renewable energy to distributed power and point of load converters.

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The things we are doing in that space are helping across the board. We are also closely following the growth of hybrid vehicles. Our automotive business is focused on power train applications, so we have a strong position in ignition and steering and we also deliver automotive power modules. We’re looking at ways to use our technology to help make cars more efficient—hybrid and electric cars as well as conventional cars. How would you describe the culture at Fairchild? Innovative. Steeped in history yet providing next generation solutions; innovation that will help our customers. I would say, as a company, we are very committed and care deeply about what we do. We have a strong desire to excel, both technically and financially, and we care a lot about our people. That includes our employees and our customers. We are a highly collaborative company and we are very focused on meeting the needs of our customers and offering them great value in the products that we sell them. We are also very multicultural—we have employees from every corner of the world and locations all over the world. The interaction leads to diverse thinking, which we also value very highly. We value that because innovation and creativity are very important to us. Fairchild is a leader in our industry and our goal is to remain a leader. Everyone at Fairchild is committed to the highest ethical standards and environmentally responsible behavior. Our largest core mission concerning energy efficiency is something that we get very excited about, and we value the contribution that makes to society in general. ■

INTERVIEW

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FEATUREDINTERVIEW PRODUCTS VoLTE Capabilities for Smart Phones Renesas Mobile Corporation, announced the completion of the integration of the Voice over LTE (VoLTE) capabilities for Renesas Mobile’s communication processor and slim modem platforms for LTE smart phones. Ecrio’s FlexIMS based VoLTE Client Software is now integrated and optimised in the MP5232 and SP2532 multi-mode LTE platforms paving the way for the broad supply of VoLTE Services based on the 3GPP IP Multimedia Subsystem (IMS). Renesas Mobile will be demonstrating VoLTE capabilities on the MP5232 platform at Mobile World Congress 2013 in Barcelona on both TD-LTE and FDD-LTE systems. For more information, please click here.

Single and Dual Low-Power CMOS Amplifiers The LMV601/LMV602/LMV604 are single, dual, and quad low voltage, low power Operational Amplifiers. They are designed specifically for low voltage general purpose applications. Other important product characteristics are low input bias current, rail-to-rail output, and wide temperature range. The LMV601/LMV602/LMV604 have 29nV Voltage Noise at 10KHz, 1MHz GBW, 1.0V/μs Slew Rate, 0.25mV Vos. The LMV601/2/4 operates from a single supply voltage as low as 2.7V, while drawing 100uA (typ) quiescent current. In shutdown mode the current can be reduced to 45pA. The industrial-plus temperature range of −40°C to 125°C allows the LMV601/ LMV602/LMV604 to accommodate a broad range of extended environment applications. For more information, click here.

DAB Receiver Enables SDR Maxim Integrated Products, Inc. (NASDAQ: MXIM) today announced the MAX2173 RF to Bits® tuner for digital audio broadcast (DAB) applications in automobiles and other mobile DAB/FM products. The industry’s first RF to Bits DAB/FM tuner integrates a radio tuner, analogto-digital converter (ADC), and digital filtering, and uses a digital I2S output to interface directly to digital signal processors (DSPs). RF to Bits radios will enable system designers to implement baseband processing using off-the-shelf DSPs. This level of integration eliminates numerous external components associated with traditional RF tuners to reduce cost, BOM count, and space. For more information, please click here.

High Density Thyristor Module Platform IXYS Corporation announced a new bipolar module platform for high power applications. The new ComPack family represents a compact package with the highest power density. The ComPack design is resulting from the implementation of the newest assembly methods in combination with the proprietary ‘power metallization chip’ technologies of IXYS. Advancement in the module design as well as the silicon die technology leads to a userfriendly product that fulfills the highest needs in reliability and functionality. The modules have a rated current of 600 Amperes per leg, improved surge rating and a maximum junction temperature of 140 Deg C. For more information, please click here. Visit www.eeweb.com

EEWeb PULSE FEATURED PRODUCTS Fiber Optic Receiver for 50 MBaud MOST AFBR-2013 Receiver are designed to receive up to 25MBit/s optical data which are biphase coded (up to 50Mbaud). They are packaged in 4-pin transfer molded, low-cost packages ready for assembly into MOST® plastic fiber optic connector receptacles. Output data has TTL switching levels, compatible with MOST® Network Interface Controller ICs. These optical components are specified for operation over a -40°C to +95°C temperature range, and reliability requirements of automotive applications. It is allowed to process the AFBR-2013 devices with reflow soldering. In the absence of data activity, the receiver switches to very low power mode. For more information, please click here.

2G/3G/4G Multiband LTE Transceiver Chip Fujitsu Semiconductor Wireless Products, Inc. (FSWP) today announced that its second LTE multimode product, the MB86L11 2G/3G/4G transceiver, is shipping in commercial quantities. The MB86L11 is a single chip multiband, multimode transceiver that supports all wireless communication modes including LTE (FDD & TDD), HSPA+, DC-HSPA, WCDMA, GSM, EDGE, CDMA and TD-SCDMA. The MB86L11 transceiver incorporates many advanced features, including envelope tracking (ET) and antenna tuning (AT). For more information, please click here.

14.2W/in3 Power Density in T8 LED Driver Power Integrations announced two new reference designs describing high-efficiency, non-isolated, high-power-factor (PF) LED drivers for T8 tubes. The designs feature low component count and leverage simple magnetics and single-sided boards yielding industry-leading power densities of 14.2 W/in³. Based on the LNK460KG LED driver from Power Integrations’ LinkSwitch-PL family of ICs, the circuits detailed in DER337 (high-line) and DER-345 (low-line) use single-stage non-isolated topologies which result in a profile of only 8 mm – small enough to be mounted behind the LEDs in the T8 tube. T8-tube reference designs describing high-efficiency, non-isolated, high-power-factor (PF) LED drivers. For more information, please click here.

Wireless Power Transmitters Integrated Device Technology, Inc. announced the industry’s most integrated wireless power transmitter solutions optimized for the Wireless Power Consortium (WPC) Tx-A5, Tx-A6, and Tx-A11 configurations. The new products expand IDT’s portfolio of WPC Qi-compliant magnetic induction transmitters with solutions optimized for single-coil 5 V and three-coil 12 V applications. The IDTP9035 and IDTP9036 are highefficiency, feature-rich wireless power transmitters. The IDTP9035 is designed to meet the requirements of the WPC Tx-A5 and Tx-A11 (5 V) specifications, while the IDTP9036 is designed to meet the WPC Tx-A6 (12 V) specification. The IDTP9035 is optimized for a single-coil configuration with a standard 5V supply input, allowing customers to reduce their bill-of-materials (BOM) with cost-effective, low-voltage power adaptors. For more information, please click here.

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FEATUREDINTERVIEW PRODUCTS

World’s lowest power capacitive sensors with auto-calibration NXP is a leader in low power capacitance touch sensors, which work based on the fact that the human body can serve as one of the capacitive plates in parallel to the second plate, connected to the input of the NXP capacitive sensor device. Thanks to a patented auto-calibration technology, the capacitive sensors can detect changes in capacitance and continually adjust to the environment. Things such as dirt, humidity, freezing temperatures, or damage to the electrode do not affect the device function. The rise of touch sensors in modern electronics has become a worldwide phenomenon, and with NXP’s low power capacitive sensors it’s never been easier to create the future.

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s the company has grown, Magna-Power has brought more and more processes in house for manufacturing power. “We believe that vertical integration allows us to not only maintain higher quality,” Pitel told us, “but also control lead times and also our costs involved.” One of the major things about these programmable power products is that they’re all configurable, meaning that they are built to order with the standard models also offered. “Today, at MagnaPower, we do all of our own transformer and inductor winding,” Pitel explained. “We have our own sheet metal operations, we do power coating, we manufacture our own heatsinks, we do PCB assemblies, we even manufacture our own magnetic cores for our transformers…” and the list goes on.

SL Series The latest product from Magna-Power is the SL series product, which provides programmable DC power from 1.5, 2.6, and 4 KW in a 1U package. The SL series is a power supply that pushes the density and power into a single 1U package. Pitel stated that, “Magna-Power has made a significant leap in the available 1U power density for programmable DC power supplies.” With Magna-Power’s growth, the company has broken into

a market where there are a lot more applications with a significantly higher volume. “It’s really required us to scale up our resources and get to a point where we can build a 1U product and really make a splash,” Pitel explained.

SL Specs The SL series has a variety of models that are all single output DC power supplies. There are 70 different models available with voltage ranges from 0 to 5 volts, up to 0 to 1,000 volts. It also has a current range from 1.5 amps to 250 amps, so there is a broad spectrum of different voltages and currents available. Just last year, Magna-Power introduced a high accuracy controller to provide highly accurate measurements for these supplies. Pitel recalled being on site with a client and his response to seeing external power meters taking all of their measurements; “I told them that they’re spending a small fortune on coupling power meters with every single power supply.” The client told Pitel that they were doing so because the accuracy from programmable DC power supplies just wasn’t high enough. Magna-Power responded directly to this problem. “In our latest generation of products,” Pitel told us, “we increased our programming accuracy nearly 10-fold—it’s now +/- 0.075% for both voltage and current.”

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SPECIAL FEATURE

“In our latest generation of products,” Pitel told us, “we increased our programming accuracy nearly 10-fold.”

Controlling the Device Every power supply from Magna-Power comes with three ways of programming it. One way is by using the front panel control knobs, which is for very basic operations. Another way is by using the 37 isolated analog and digital I/Os, so users can program it from an analog 10V signal and tie it in with a PLC. These supplies also come with a computer interface as well, which offers LXI-certified TCP/IP Ethernet and IEEE 488 GPIB. Recently, MagnaPower certified its products with the new LXI 1.4 standard, which supports the same mDNS standard that Apple made popular with Bonjour. If developers want to integrate controlling one of these devices into a customized software they have developed, Magna-Power also provides support for interfacing the programming languages. “We invested quite a bit into developing IVI drivers,” Pitel stated, “which is basically a universal driver that is supported in a wide variety of different programming environments.” These different environments include LabView, LabWindows, and Visual Studio, providing a full command set for the power supply. Users can access all of those commands in the power supply and any of these programming environments, which is made simple using the IVI driver.

All of Magna-Power’s power supplies under 1,000 volts come with remote sense functionality, so users can hook up load wires and have a high impedance remote sense line to attach as well. Pitel told us that the leadless remote sense function is becoming very popular among their customers. “Consider an application where someone is powering an underwater vehicle and they have a 1,000foot cable powering it up, which can be pretty daunting. The nice thing is, you can have a 1,000-foot cable and have the impedance known through the leadless remote sense function.” Conveniently enough, if the user knows the impedance of the cable, they can compensate for that automatically within the power supply. Magna-Power’s various programmable power devices seem to directly respond to the customer’s needs. Whether it’s hearing about user’s problems from being on-site or by analyzing the current limitations of programmable power devices on the market today, Magna-Power pushes the limits of power devices so that they’re one step ahead of the rest. ■

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DDR4 Design Considerations Mike Micheletti Product Manager Teledyne LeCroy

DDR4

represents a substantial upgrade to JEDECâ&#x20AC;&#x2122;s dynamic random access memory (DRAM) standard, with numerous changes designed to lower power consumption while delivering higher density and bandwidth within the memory subsystem. DDR developers are targeting this new technology at a range of applications from high density blade servers, to high performance workstations and power-conscious mobile devices. Deploying general purpose memory in systems with specialized power and performance requirements means the designer must evaluate the cost and benefits of these new DDR4 features within the context of the target application. New techniques for analyzing and testing DDR operation in a live systems will be essential to gain this visibility. Balancing the promise of faster memory IO with the goal of lower power consumption at the system level will require tuning of features, timing, and design.

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TECH ARTICLE

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DDR4 is expected to deliver significantly higher performance, via faster data transfer rates reaching at least 3200 MT/s over time. In addition, the new specification introduces a number of enhancements used to improve both power efficiency and reliability. These features can add significant verification complexities for system designers, firmware developers and software designers. As one would expect, engineers are expected to march through the natural progression of the technology validation including signal integrity, timing analysis and specification compliance, performance tuning and power management modeling. This article explores methods to verify initial design and compliance with the new DDR4 JEDEC specifications along with techniques used to take advantage of DDR4 features and maximize system performance. While there are many potential instruments that can be used, a new generation of dedicated DDR bus analyzers now provide comprehensive timing and protocol analysis, making them an important tool for accelerating DDR4 system validation and design. Substantially lower in cost than a logic analyzer, these systems can be used to qualify different memory DIMM components, as well as help sustain engineering groups as they verify system operations over the entire product life cycle.

DDR4 Technical Overview Table 1 provides a brief comparison between DDR4 and DDR3 memory technology. DDR4, initially targeted for the server market, adopts a number of enhancements intended to deliver better performance, power-savings, and RAS (reliability, accessibility and serviceability) versus DDR3. These enhancements present unique and significant performance improvement and power reduction opportunities. Special attention must be taken when setting DDR4 power savings parameters so that suitable performance levels are still achieved.

DDR4â&#x20AC;&#x2122;s new memory interface employs â&#x20AC;&#x153;pseudo-opendrainâ&#x20AC;? (POD) termination where memory cells can store a logical 1 without consuming power. POD relies on switchable, on-die termination instead of a separate resistor pull up. Parallel-terminating the receiver at the far end means the DDR4 DIMM only consumes power when the Vdd rail is pulled low to represent logical zero. The anticipated higher transfer rates in DDR4 mandate tighter timing margins to support normal variations in memory DIMMs. DDR4 also offers programmable Command-to-Address Latency that can be used to improve system power efficiency. Expanded role of MRS and the introduction of bank groups make memory controller designs more complex. These factors are expected to drive changes in memory controller designs and associated IP in order to support DDR4. Data transfer rates for DDR4 and DDR3 should overlap for the foreseeable future, with DDR4 delivering a longer performance runway. It is quite conceivable for a DDR4 platform to deliver moderate power savings versus a comparable DDR3 design, but potentially at the expense of lower memory bandwidth under certain DDR4 operating parameters. System designers need to design highly tuned, balanced platforms that leverage the power saving and RAS enhancements of DDR4.

Managing DDR4 JEDEC Specifications The JEDEC specification targets specific timings for DDR4 memory controllers and their associated DRAMs. The majority of these are described as minimums, along with a minimum time before subsequent events are allowed. One of the primary JEDEC specification objectives is to avoid memory collisions caused by overlapping commands. Memory controllers and DRAMs therefore must be designed and tested for adherence to the JEDEC specifications across process, voltage, and temperature

Table 1: DDR4 vs. DDR3 key enhancements

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TECH ARTICLE

Figure 1: Evaluating and analyzing timing violations using protocol analyzers.

variation during their functional testing with Automated Test Equipment (ATE). Additional variables introduced at the system level, such as DIMM design, socket, and motherboard design and layout, can contribute to timing violations at a system level, and must be taken into consideration. DDR4 introduces the concept of Bank Groups that allow the system designer to build interleaved memory arrays down to the individual device level. For smaller systems, which may have only a single memory device, this Bank Group feature can offer substantial benefits. For example, one bank group can receive a series of pipelined commands for its upcoming data transfers. Once the first Bank Group starts its actual data transfers, another Bank Group can be initialized with its separate set of pipelined commands. After the first Bank Group completes its data transfers, the second Bank Group can initiate its data transfers, since it has already received its set of pipelined commands. In many cases, this Bank Group command pipelining can significantly reduce the impact of memory device delays, as shown below. A new generation of dedicated DDR4 protocol analyzers, such as the Teledyne-LeCroy Kibra 480 system, provide automatic detection of JEDEC timing violations by monitoring memory IO on a live system. Validation engineers can leverage the flexibility of a protocol

analyzerâ&#x20AC;&#x2122;s trigger state machine and its deeper recording memory to set up more complex triggering scenarios, or optionally use the analyzer in conjunction with an externally triggered oscilloscope for deeper signal integrity evaluation and analysis. Figure 1 illustrates a DDR4 timing violation captured from a series of sequential accesses to the same DRAM bank group. The JEDEC tRRD_L specification requires a minimum delay of 6 clock periods between subsequent accesses. In this case, the tRRD_L specification has been violated since only 5 Clock intervals between activates are found in the captured trace. The memory controller needs to be adjusted so that the tRRD_L specification is properly met. In addition to the spec violation, this violation may also cause bus contention on the data lines. Further examination of the lower pane in Figure 1 (Traffic Summary) illustrates the total number of timing violations in the captured traffic. Note that the traffic violation tool tip in the waveform pane highlights the expected timing interval (i.e. timing specification) versus the actual measured timing. Some of the timing violations can be attributed to poor design issues in the memory controller, while others could be caused by signal integrity marginalities introduced at the board level or sequence/ pattern specific failures. As these violations are flagged, they point out problem areas for the memory system designer to investigate. Visit www.eeweb.com

EEWeb PULSE DDR4 Configuration starts with MRS Commands DDR4 introduces four new MRS commands to help support new features. Many of these new features are optional, allowing system integrators to turn them on and off based on the application. Making systems more configurable will involve verifying that specific functions are enabled by viewing the MRS commands. A critical feature in DDR4 is the DQ Training with MPR that is initiated via the MR3 immediately after power on. This provides pre-defined registers that can be used to choose fixed or custom training patterns, which will be read in a controller specified order. Most memory designers will concede that DDR4 will not reach the expected performance without receiver calibration. The MR3 payload (Figure 2) shows the Address lines (A2) is used to enable MPR training and the (A12 –A11) are used to identify the format of the MPR pattern. Using the DDR4 Bus analyzer, it’s possible to trigger, capture, and decode the MR3 command. “MPR Page Selection:0” specifies that the DIMM should use the Multi Purpose Register 3 – page zero default patterns for training and transmit them in serial format. Toggling the “Dataflow from MPR” option programs the DRAM to respond with the specified pattern on the next READ

command instead of from the memory array. Back-to-back reads can then be used to “tune” the receivers to operate with the highest signal integrity. Teledyne LeCroy’s Kibra 480 analyzer provides developers with unique ability to “Follow MRS Commands” on the fly. Enabling this option allows the analyzer to adjust the JEDEC timing intervals in real time. In the event the memory controller sends MRS commands that change specific parameters, the Follow MRS Commands option prevents the Kibra from detecting and reporting false errors (i.e.: MRS commands that toggle DQ Training mode or change the burst length). The timing analysis methods discussed above allow designers to quickly identify timing violations on an individual system basis. However, robust system designs should be able to accomodate platform, component, and DIMM variations. This requires a deeper characterization of critical timing specifications to ensure sufficient system design tolerances. As memory systems increase in speed and complexity, many controller and DIMM combinations may perform better than the JEDEC specification. Memory system designers need visibility into the system configuration and performance, as opposed to simple specification compliance. Dedicated bus analyzers, like the Teledyne-LeCroy Kibra 480 system, offer excellent flexibility to selectively sweep and measure critical timing

Figure 2: Capture and decoding of MRS commands facilitates testing and verification of DDR4 subsystem configuration

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TECH ARTICLE since interleaving data between bank groups increases the risk of collisions as DDR4 systems pivot between CCD-S and CCD-L. This effort requires a high degree of visibility into the traffic patterns across the banks and bank groups. Figure 4 illustrates a DDR4 platform without DDR4 bank group tuning. One can easily observe that memory access is sparsely distributed, with long periods of inactivity where the banks are left open for long periods of time.

Figure 3: Timing sensitivity analysis versus JEDEC specifications.

parameters, helping measure the actual system design timing margins, as seen in Figure 3. Of unique value, timing analysis can be performed on previously captured traffic by simply modifying timing parameters and rerunning the analysis software on a personal computer, allowing the protocol analyzer to be freed up for more critical debug activities.

Figure 5 shows the same platform during a highly tuned memory access taking advantage of the performance advantages of bank groups with demonstrably quicker memory access. â&#x2013;

Maximizing DDR4 System Performance As mentioned earlier, while DDR4 is designed to provide significant power and performance advantages over DDR3, in the interim their transfer rates are likely to overlap, giving the more mature, highly tuned DDR3 designs a performance advantage (for the time being). Given the near term anticipated cost disadvantage of DDR4 memory subsystems, early adopters should pay special attention to tuning their platform in order to maximize performance.

Figure 4

DDR4 architecture introduces the concept of two or four selectable bank groups, a unique feature that can be used to boost the performance of DDR4 platforms. This allows for separate activation, access, and refresh of each unique bank group, improving overall memory efficiency and bandwidth. DDR4 platforms can only achieve the highest throughputs with consecutive reads and writes when targeting different bank groups, allowing for lower latencies on commandto-command timing (tCCD-S) and faster burst access. New memory controller designs taking advantage of the DDR4 bank groups must be thoroughly validated

Figure 5

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Desi OF TDC CONVERTER ARCHITECTURES

IN 80NM CMOS TECHNNOLOGY

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part

& Anal

ign

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lysis

ABSTRACT:

By:

Umanath Kamath, Cypress Semiconductors Javier Rodriguez, Strukton Rolling Stock

The first part of this article detailed the various topologies for realizing a time-to-digital converter with their trade-offs. This part will go through implementation of a TDC in 80nm CMOS process. The article concludes with results of the transistor level implementation giving the reader an understanding of the method while also appreciating the various applications to which it can be applied.

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From this table we can conclude the following:

Figure 1: 2-D Vernier matrix figures of merit

Continued from Part 1

5. SYSTEM OVERVIEW After choosing the TDC structure, we started working on our design implementation following a top-down approach. From our point of view, and due to the large degree of freedom available for this design, this was the most logical starting point. 5.1. Matrix structure

To achieve a square matrix, and therefore a homogeneous load for every delay element, we need a 17×17 matrix. However, this structure will yield an unacceptable number of dummy structures (88.93% of the matrix will consist of dummy structures). Hence this matrix layout was discarded. There is an interesting set of solutions, yielding a minimum number of columns (10 columns for 5, 6 and 7 rows). Naturally, the number of dummy structures increases with the number of rows. However, we finally chose the 7×10 matrix configuration, as shown in Figure 2, since the dummy increment is not very large and the row-column ration is closer to 100% among those three configurations.

Choosing an appropriate matrix structure was the first design issue we had to face. As already mentioned, there are two main considerations to take into account: Delay y

• Dummy structure minimization within the matrix, since they consume power and contribute to the overall design area.

• Delay stage loading since a homogeneous load for every delay stage will contribute to an easier design and a better resolution controllability. As discussed before, a bigger matrix yields a larger number of dummy structures but a more homogeneous capacitive load for both X and Y delay chains, as the row-column ratio approaches 1 and the matrix becomes square, making resolution easier to set. A smaller matrix will have the opposite effect, thus yielding a smaller number of dummy structures but making resolution harder to set. Keeping these two design parameters in mind, we derived the mathematical expressions for calculating them. Afterwards, we built the following table which summarizes all the possible solutions for our 32 stage 2-D Vernier TDC design, allowing us to analyze the problem and find the best solution:

Delay x

Figure 2: 7x10 TDC matrix structure

5.2. DELAY CHAINS As seen in the previous chapters, the Vernier delay line architecture uses two different delay chains. While in the linear Vernier delay line architecture these chains only differ in the nominal propagation delay of each element (i.e. the propagation delay measured when the other input signal is tied to ground), 2-D Vernier delay chains also differ in the number of elements they are made of. For instance, a 32 stage linear Vernier TDC would need two delay chains of 32 delay elements each, while our 2-D Vernier TDC would need only one chain of 10 delay

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elements (X delay chain) and another one of 7 delay elements (Y delay chain). For the delay stages within the chains, we decided to use non-inverting buffer structures as the main building blocks. These structures yield a worse propagation time than a single inverter, but they provide the delay comparison and encoding stages with a very simple time information format. For this purpose, we created two different components within our library, called BUF_X and BUF_Y.

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capacitive loading for both the X and Y delay chains. Besides, we also included an inverting buffer at each output, as recommended in [1], making this device less sensitive to output loading variations and preventing the design from unwanted non-linear behavior. S#

Since the Y delay chain has to be faster than the X delay chain but its capacitive load per delay element is, by construction, larger than the Xâ&#x20AC;&#x2122;s, it makes sense to initially increase the size of the BUF_Y transistors. However, since we are only dealing with low-to-high transitions, this can be achieved by just increasing the pMOS transistor in the second inverter within the BUF_Y structure. For the BUF_X component we initially set to minimum size for both pMOS and nMOS transistors.

Figure 3: Delay comparator (gate level)

Besides setting the minimum size, we added an extra delay element at the end of both delay chains. This final delay element was left open (actually it is driving a 1GÎŠ resistor to avoid Cadence WARNING messages) and its only goal is to balance every capacitive load within the chain.

Figure 4: S-R latch truth table

We also included an extra input delay stage on both chains, called FIX_DELAY within our library. These structures were used to provide a rise and fall time independent signals to the delay chain during the first design tests. While FIX_DELAY elements remained unchanged through the design process, BUF_X and BUF_Y buffers were resized and optimized to achieve the desired resolution. 5.3. Delay comparators

Special care has to be taken when connecting the feedback and input signals to the NAND pull-down network due to data dependent delay. Indeed, the nominal propagation delay of each element within the chain can be affected by the S-R latch current state, introducing non-linear effects. In particular, for this TDC architecture, this effect becomes quite significant since there are several S-R latches connected to the same delay element output. Figure 5 shows the two possible configurations. VDD

VDD FB2

FB1

FB2

FB1

The time difference between the START and STOP signals is measured by the use of several memory elements which capture the moment when the START signal is surpassed by the STOP signal. Following this principle, a 32-bit pseudo thermo-code format is generated by the TDC, where the delay information is kept as the transition from 1 to 0. Finally, this code is passed to the 5-bit encoding circuit.

Figure 5: Delay comparator (transistor level)

Choosing among all the available memory elements for this task, we followed the recommendations given in [1] and used a NAND gate based S-R latch as the basic delay comparison element. The main advantage which presents this structure is its symmetry for both S and R signals, helping us to achieve a more homogeneous

We obtained some interesting results while testing both configurations; which are shown in Figure 6. In particular, this figure shows the propagation delay for each delay element within the X delay chain for both configurations. We used for this purpose a 10 ps resolution configuration and a time delay of 160 ps between the START and STOP

FB1

FB2

FB1 FB2

FB2

FB2 FB1

FB1

GND

GND S#

Config 1

Config 2

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signals. Therefore, the STOP signal will catch the START signal in the 16th delay comparator (2nd row, 3rd column). As can be seen, the propagation delay for the first configuration remains constant for the first and second columns, but it starts to decrease linearly after that due to a change in the capacitive load (data dependent delay). This is, of course, an undesired effect which must be avoided to prevent a non-linear behavior. On the other hand, by using the second configuration, each delay element within the X delay chain achieves a more uniform propagation delay and itâ&#x20AC;&#x2122;s almost data independent. Despite the fact that the use of this S-R latch configuration increases the nominal propagation delay, it is not a big issue and it can be readjusted by sizing the delay elements. Therefore we will be using the 2nd configuration in our SR_LATCH library component. Config 1

Nom. Config 1

Config 2

Nom. Config 2

Once the main design features have been described in the previous chapter, now we present all the different strategies we followed to achieve our current design. 6.1. Area minimization Since our design was quite large in terms of the number of transistors, area minimization is a critical goal which allowed us to improve our design performance. In particular, we focused on the TDC matrix structure and devised several ways to improve its area consumption.

6.1.1. Y chain load reduction We realized that for each row within the matrix, there are at most five out of ten useful devices for delay comparison. Hence, the Y delay chain had an excessive loading, which affected both the acquisition time and the circuit area for the same resolution. However, as we presented in the previous chapter, our S-R latch configuration made the circuit almost data independent. This feature allowed us to disconnect them from the Y chain and tie them to ground without harming the circuit performance. Figure 7 shows the TDC matrix after performing this optimization step, where red dots represent the S-R latches which were disconnected from the Y delay chain. However, there were still three dummy S-R latch structures left to balance the capacitive load.

83 81 79

Propagation Delay (ps)

6. TUNING THE DESIGN

77 75 73 71 69 67

65 X1-X2

X2-X3

X3-X4

X4-X5

X5-X6

X6-X7

X7-X8

X8-X9

X9-X10

Delay Stage (X delay chain)

This concludes the basic description of our TDC delay comparator. However, as will be discussed in chapter 6, and due to the amount of dummy S-R latches introduced by the TDC matrix, we proceeded to substitute them for more optimal structures which roughly present the same capacitive loading, helping us to save area and power. Hence a new library component, called DUMMY, was created. 5.4. Readout encoder Finally, we focused on the 32 to 5 encoder needed for the readout circuit. Since the existing/available testbench provided us with a quite good encoder, we decided to spend more effort into the matrix optimization.

Delay y

Figure 6: Data dependent analysis for both configurations

Delay x

Figure 7: Y delay chain optimization

The, Y chain load was greatly reduced, thus reducing the propagation delay for each delay element within the chain. Furthermore, the propagation delay for each delay element within the X delay chain remained almost constant due to our S-R latch structure.

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6.1.2. Dummy structures

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VDD

After the Y chain optimization, most of the S-R latches had one of their input tied to ground. Looking at their gate level schematic, it was easy to conclude the following: • Since one NAND gate had an input tied to ground, its output is tied to 1. This output is used as one of the inputs of the other NAND gate within the component. • Removing the former NAND gate along with its associated inverter reduced the circuit area maintaining a constant propagation delay for the X chain delay elements. • However, since these structures do not commute, dynamic power consumption was not affected by this optimization. With these ideas in mind, we obtained the following structure for our DUMMY component, which is basically a capacitive load:

GND S#

Figure 9: Final S-R latch component (transistor level)

6.2. Resolution optimization As shown in section 3.2, our TDC resolution is given by the following relationships:

The following table summarizes all the relevant parameters needed for a given resolution ranging from 5 to 10 ps:

VDD 1 R#

1 Figure 10: TDC resolution chart

GND Figure 8: Dummy component (transistor level)

NOTE: A further area optimization can be easily done by removing one of the pMOS transistors within the NAND gate since it is always OFF. However we did not realize that until later, we could not include it in the submitted TDC design. 6.1.3. S-R latch optimization Our final area improvement dealt with the active S-R latches themselves. As we only used one of the device outputs, we just removed the unused output, along with its associated inverter. By introducing this modification, we did not observe any major change in the delay element’s propagation delay.

Therefore, by just sizing the delay elements within both delay chains we can achieve any required resolution. However, our TDC architecture presents two major drawbacks in comparison with the linear Vernier delay line architecture: • Our resolution is totally dependent on the propagation delay of each delay elements, as can be seen in the table above. Ignoring this fact will cause the system to behave in an unpredictable and highly non-linear way. Hence bigger delay elements will be needed if aiming for high resolution. • Each delay element has to drive a larger load, due to the matrix configuration. Again, sizing becomes a problem for a given resolution, limiting our design space. Due to this, we aimed for a 9 ps resolution, which is slightly better than the proposed in the midterm report and does not imply too large transistors.

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6.2.1. Sizing procedure For delay elements sizing we used the approach from [5], using the following circuit:

S CL

Figure 11: Delay element sizing problem

, which follows the equation:

To solve this equation, we first found the values of tp0 and the load ratio by simulating the circuit for two different values of S. Finally, knowing these two parameters, we could find the value of S for our desired tp. The following table shows the final values for the transistors within the delay chains:

We could not complete all of them, but would like to include them for reference: • The given encoder is mostly responsible for power consumption for high output codes. By increasing its complexity, power can be reduced for these stages, yielding a lower average energy and power consumption. • Acquisition time can also be improved by just using a different encoder architecture which balances the output signals code load. Increasing the S-R latch output inverter can also help to reduce the system acquisition time. • Better resolution can be achieved by further sizing both delay chains, as described in section 6.2.

ACKNOWLEDGEMENTS: The authors wish to acknowledge the references from the course notes of Digital IC Design course at Delft University of Technology. They also are grateful for various discussions and inputs from Prof.Nick van der Meijs during the course of the project.

8. REFERENCES Figure 12: Delay chain sizing summary

NOTE: Sizing could be further improved since the first inverter always performs high to low transitions and the second inverter always performs low to high transitions. Therefore, the X BUFFER 2nd inverter nMOS width could have been left to 120 µm without affecting resolution.

7. FINAL RESULTS AND CONCLUSIONS With this article, we have shown the procedure we followed to implement our submitted TDC design. This design achieves a relatively high time resolution while area and power consumption has been reduced in comparison with the original design, described in [1]. In this sense, our design meets all the requirements described in section 2. To conclude, a summary with all the relevant results is provided in section 9.

[1] Vercesi, L., Liscidini, A., Castello, R., “Two-Dimensions Vernier Time-to-Digital Converter”, IEEE Journal of SolidState Circuits, August 2010, pp 1504-1512. [2] Chen, P., Liu, S. I., Wu, J., “A CMOS pulse shrinking delay element for time interval measurement”, IEEE Transactions on Circuits and Systems II,: Analog and Digital Signal Processing, September 2000. [3] Staszewski, R. B., Vemulapalli, S., Vallur, P., Wallberg, J., Balsara, P. T., “1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS,” IEEE Transactions on Circuits and Systems II: Express Briefs, March 2006. [4] Henzler, S., Koeppe, S., Lorenz, D., Kamp, W., Kuenemund, R., Schmitt-Landsiedel, D., “A Local Passive Time Interpolation Concept for Variation-Tolerant HighResolution Time-to-Digital Conversion”, IEEE Journal of Solid State Circuits, July 2008. [5] Rabaey, J. M., Chandrakasan, A., Nikolic,B., “Digital Integrated Circuits, a Design Perspective” 2nd edition, Prentice Hall, 2006.

7.1. Challenges and future work There are some further issues which can be easily optimized and can lead our design to better performance.

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9. PROJECT OVERVIEW 9.1. Project summary table

Parameter

Value

Architecture

2-D Vernier

Optimized parameter

Area & Power

Voltage supply

Average resolution

8.96 ps

Average resolution (slow)

11.68 ps

Average resolution (fast)

6.93 ps

Area/min. INV size area

340.375

Total Power

2.58 mW

Average Power

0.08 mW

Total Energy

6.462424 pl

Average Energy

0.201951 pl

Acquisition time (50%)

1.044 ns

Acquisition time (90%)

1.23 ns

Advantages

High linearity, low power

Drawbacks

High area overhead

Targeted application

RF PLL

About the Authors Umanath Kamath received his Masterâ&#x20AC;&#x2122;s degree in 2012 from Delft University of Technology, Delft, the Netherlands and Bachelors degree in 2009 from M.S.Ramaiah Institute of Technology, Bangalore, India both in electronics. He is currently a Senior Design Engineer with Cypress Semiconductors. He has held visiting positions during his studies with IMEC and CMOSIS in Belgium and Honeywell Research Labs in India. His interests are in the area of analog and mixed signal circuit design, low power sensor interfaces, power manag ment circuits and sigma-delta converters.

Javier Rodriguez received his Telecommunication Engineering degree from Technical University of Madrid (UPM) in 2006. After 3 years working as a R&D engineer in Spain, he obtained his MSc in Electrical Engineering (Microelectronics) from Delft University of Technology in 2012, focusing on circuit design automation and verification techniques. He is currently working at Strukton Rolling Stock as a Software Engineer.

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