TECH ARTICLE
Figure 1: Evaluating and analyzing timing violations using protocol analyzers.
variation during their functional testing with Automated Test Equipment (ATE). Additional variables introduced at the system level, such as DIMM design, socket, and motherboard design and layout, can contribute to timing violations at a system level, and must be taken into consideration. DDR4 introduces the concept of Bank Groups that allow the system designer to build interleaved memory arrays down to the individual device level. For smaller systems, which may have only a single memory device, this Bank Group feature can offer substantial benefits. For example, one bank group can receive a series of pipelined commands for its upcoming data transfers. Once the first Bank Group starts its actual data transfers, another Bank Group can be initialized with its separate set of pipelined commands. After the first Bank Group completes its data transfers, the second Bank Group can initiate its data transfers, since it has already received its set of pipelined commands. In many cases, this Bank Group command pipelining can significantly reduce the impact of memory device delays, as shown below. A new generation of dedicated DDR4 protocol analyzers, such as the Teledyne-LeCroy Kibra 480 system, provide automatic detection of JEDEC timing violations by monitoring memory IO on a live system. Validation engineers can leverage the flexibility of a protocol
analyzer’s trigger state machine and its deeper recording memory to set up more complex triggering scenarios, or optionally use the analyzer in conjunction with an externally triggered oscilloscope for deeper signal integrity evaluation and analysis. Figure 1 illustrates a DDR4 timing violation captured from a series of sequential accesses to the same DRAM bank group. The JEDEC tRRD_L specification requires a minimum delay of 6 clock periods between subsequent accesses. In this case, the tRRD_L specification has been violated since only 5 Clock intervals between activates are found in the captured trace. The memory controller needs to be adjusted so that the tRRD_L specification is properly met. In addition to the spec violation, this violation may also cause bus contention on the data lines. Further examination of the lower pane in Figure 1 (Traffic Summary) illustrates the total number of timing violations in the captured traffic. Note that the traffic violation tool tip in the waveform pane highlights the expected timing interval (i.e. timing specification) versus the actual measured timing. Some of the timing violations can be attributed to poor design issues in the memory controller, while others could be caused by signal integrity marginalities introduced at the board level or sequence/ pattern specific failures. As these violations are flagged, they point out problem areas for the memory system designer to investigate. Visit www.eeweb.com
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