PULSE The example starts by importing the xsdutio class from the xstools package. Then it creates a USB-to-DUT (XsDutIo) object to communicate to the HostIoToDut module in the FPGA. During creation, the object is told that the adder has two, eight-bit inputs, an eight-bit sum output, and a onebit carry output.
to the address, control and data inputs of a RAM while connecting the RAM data outputs to the module's response input ports. But then you would have to issue multiple commands to write the address and data, strobe the read/write controls, and read back the data from the RAM. That would be slow and error-prone.
The adder is iteratively given 100 test cases where random bytes are assigned to the two inputs. The exec function of the adder object performs the following operations:
For that reason, the HostIoToRam module was built for interfacing to RAMs and other components with a register type of interface (like a UART).
1. It takes the two bytes for the adder inputs and converts them to bit strings.
The I/O interface between the module and a RAM consists of the following signals:
2. It concatenates the two, eight-bit strings and sends them to the HostIoToDut module in the FPGA along with a WRITE opcode. This causes the module to apply the two bit strings to the inputs of the adder.
Clk: A clock input so the HostIoToRam module can synchronize its operations to the RAM clock (if it's a synchronous type).
3. It then sends a READ opcode to the HostIoToDut module and reads back nine bits from the adder.
Data: The bidirectional RAM data bus.
4. It splits the nine bits into an eight-bit sum and a one-bit carry and returns these as two, individual bit strings.
Write: The RAM write control line.
The sum and carry bitstrings are converted to unsigned integers and combined to get the final sum from the adder. Then this is compared to the sum calculated within the Python script to detect whether any errors occurred.
Address: The RAM address bus.
Read: The RAM read control line.
Done: An input for the acknowledgement signal from the RAM when the memory operation has completed.
It's easy to extend this example to test multiple DUTs in an FPGA by just creating additional XsDutIo class objects with distinct IDs (and instantiating more HostIoToDut modules in the FPGA, of course). Since this is done with Python, you have access to all the other Python libraries for writing your testing scripts. You can even put GUI front-ends on them if that's your thing.
Extending the Concept to RAMs While it's nice to have the HostIoToDut module to observe and control the digital circuitry inside an FPGA, there's one common type of design entity that it doesn't really support: RAM-like components. Of course, you could instantiate a HostIoToDut module and connect the test vector output ports
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Figure 4: HostIoToRam Interface